DS1878T+T&R Maxim Integrated Products, DS1878T+T&R Datasheet - Page 23

• Manufacturer Part Number: DS1878T+T&R
• Description: IC CTLR SFP W/DGTL LDD RX 28TQFN
• Manufacturer: Maxim Integrated Products
• Type: SFP+ Controllerr

Specifications of DS1878T+T&R

• Input Type: *
• Output Type: *
• Interface: *
• Current - Supply: *
• Mounting Type: Surface Mount
• Package / Case: 28-WFQFN exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The DS1878 has an ID hardcoded in its die. Two regis-
ters (Table 02h, Registers CEh–CFh) are assigned for
this feature. The CEh register reads 78h to identify the
part as the DS1878, while the CFh register reads the
current device version.
The device controls a Maxim laser driver and limiting
amplifier over a proprietary 3-wire interface. The device
acts as the master, initiating communication with and
generating the clock for the Maxim slave device(s). It is
a 3-pin interface consisting of SDAOUT (a bidirectional
data line), SCLOUT (clock signal), and a chip-select
output (active high). Two chip selects are provided.
CSEL1OUT is active during all communications.
CSEL2OUT is only active during communications to the
limiting amplifier. By connecting CSEL2OUT to a Maxim
limiting amplifier, there is less noise induced by the
communication interface on the limiting amplifier, since
none of the laser driver communications are processed
by the limiting amplifier.
Figure 16a. TXFOUT Nonlatched Operation
Figure 16b. TXFOUT Latched Operation
(ONLY ALARM FAULTS PRESENT)
DETECTION OF TXF FAULT
3-Wire Master for Controlling
DETECTION OF TXF FAULT
the Maxim Laser Driver and
(QT ALARMS PRESENT)
SFP+ Controller with Digital LDD Interface
TXD OR TXF RESET
______________________________________________________________________________________
TXFOUT
TXFOUT
TXFOUT
Limiting Amplifier
Die Identification
The device initiates a data transfer by asserting the
CSEL_OUT pin. It then starts to generate a clock signal
after CSEL_OUT has been set to 1. Each operation
consists of 16-bit transfers (15-bit address/data, 1-bit
RWN). All data transfers are MSB first.
Write Mode (RWN = 0): The master generates 16 clock
cycles at SCLOUT in total. It outputs 16 bits (MSB first)
to the SDAOUT line at the falling edge of the clock. The
master closes the transmission by setting CSEL_OUT to
0.
Read Mode (RWN = 1): The master generates 16 clock
cycles at SCLOUT in total. It outputs 8 bits (MSB first)
to the SDAOUT line at the falling edge of the clock. The
SDAOUT line is released after the RWN bit has been
transmitted. The slave outputs 8 bits of data (MSB first)
at the rising edge of the clock. The master samples
SDAOUT at the falling edge of SCLOUT. The master
closes the transmission by setting CSEL_OUT to 0.
15:9
BIT
7:0
8
Address
NAME
RWN
Data
7-bit internal register address
0: write; 1: read
8-bit read or write data
t
INITR1/2
DESCRIPTION
Protocol
23