DS1878T+T&R Maxim Integrated Products, DS1878T+T&R Datasheet - Page 44
![no-image](/images/manufacturer_photos/0/4/417/maxim_integrated_products_sml.jpg)
DS1878T+T&R
Manufacturer Part Number
DS1878T+T&R
Description
IC CTLR SFP W/DGTL LDD RX 28TQFN
Manufacturer
Maxim Integrated Products
Type
SFP+ Controllerr
Datasheet
1.DS1878TTR.pdf
(98 pages)
Specifications of DS1878T+T&R
Input Type
*
Output Type
*
Interface
*
Current - Supply
*
Mounting Type
Surface Mount
Package / Case
28-WFQFN exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Lower Memory, Register 71h: ALARM
SFP+ Controller with Digital LDD Interface
44
71h
______________________________________________________________________________________
POWER-ON VALUE
READ ACCESS
WRITE ACCESS
MEMORY TYPE
MON3 HI
BIT 7
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
MON3 HI: High-alarm status for MON3 measurement. A TXD event does not clear this alarm.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
MON3 LO: Low-alarm status for MON3 measurement. A TXD event does not clear this alarm.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
MON4 HI: High-alarm status for MON4 measurement. A TXD event does not clear this alarm.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
MON4 LO: Low-alarm status for MON4 measurement. A TXD event does not clear this alarm.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
RESERVED
TXFS: Reflects the status of the TXF pin. The status also includes any inversion caused by the INVTXF
bit (read only).
0 = TXF pin is low (after any inversion caused by the INVTXF bit).
1 = TXF pin is high (after any inversion caused by the INVTXF bit).
FETG: Status of Internal Signal FETG. The FETG signal is part of the internal shutdown logic.
0 = FETG is low.
1 = FETG is high.
TXFINT: TXFOUT Interrupt. This bit is the wire-ORed logic of all alarms and warnings wire-ANDed with
their corresponding enable bits in addition to nonmaskable alarms TXP HI, TXP LO, BIAS MAX, and HBAL.
The enable bits are found in Table 01h/05h, Registers F8h–FFh.
MON3 LO
00h
All
N/A
Volatile
MON4 HI
2
MON4 LO
RESERVED
TXFS
FETG
TXFINT
BIT 0
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