DS1878T+T&R Maxim Integrated Products, DS1878T+T&R Datasheet - Page 53

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DS1878T+T&R

Manufacturer Part Number
DS1878T+T&R
Description
IC CTLR SFP W/DGTL LDD RX 28TQFN
Manufacturer
Maxim Integrated Products
Type
SFP+ Controllerr
Datasheet

Specifications of DS1878T+T&R

Input Type
*
Output Type
*
Interface
*
Current - Supply
*
Mounting Type
Surface Mount
Package / Case
28-WFQFN exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Table 01h, Register FAh: ALARM EN
FAh
POWER-ON VALUE
READ ACCESS
WRITE ACCESS
MEMORY TYPE
Layout is identical to ALARM
Figure 14) logic. The MASK bit (Table 02h, Register 89h) determines whether this memory exists in Table 01h or
05h.
RESERVED
SFP+ Controller with Digital LDD Interface
BITS 7:4
BIT 7
BIT 3
BIT 2
BIT 1
BIT 0
______________________________________________________________________________________
RESERVED
HBAL:
0 = Disables interrupt from HBAL alarm.
1 = Enables interrupt from HBAL alarm.
RESERVED
TXP HI:
0 = Disables interrupt from TXP HI alarm.
1 = Enables interrupt from TXP HI alarm.
TXP LO:
0 = Disables interrupt from TXP LO alarm.
1 = Enables interrupt from TXP LO alarm.
RESERVED
00h
PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C)
PW2 or (PW1 and RWTBL1C)
Nonvolatile (SEE)
1
1
RESERVED
in Lower Memory, Register 72h. Enables alarms to create internal signal FETG (see
RESERVED
HBAL
RESERVED
TXP HI
TXP LO
BIT 0
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