PCA9670BS,118 NXP Semiconductors, PCA9670BS,118 Datasheet - Page 18

• Manufacturer Part Number: PCA9670BS,118
• Description: IC I/O EXPANDER I2C 8B 16HVQFN
• Manufacturer: NXP Semiconductors

Specifications of PCA9670BS,118

• Package / Case: 16-VQFN Exposed Pad, 16-HVQFN, 16-SQFN, 16-DHVQFN
• Interface: I²C
• Number Of I /o: 8
• Interrupt Output: No
• Frequency - Clock: 1MHz
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Includes: POR
• Logic Family: PCA9670
• Number Of Lines (input / Output): 8.0 / 8.0
• Operating Supply Voltage: 2.3 V to 5.5 V
• Power Dissipation: 400 mW
• Operating Temperature Range: - 40 C to + 85 C
• Input Voltage: 5.5 V
• Logic Type: I/O Expander
• Maximum Clock Frequency: 1 MHz
• Mounting Style: SMD/SMT
• Number Of Input Lines: 8.0
• Number Of Output Lines: 8.0
• Output Current: 50 mA
• Output Voltage: 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935282714118; PCA9670BS-T; PCA9670BS-T

NXP Semiconductors
13. Dynamic characteristics
Table 6.
V
[1]
[2]
[3]
[4]
PCA9670_2
Product data sheet
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
t
Port timing; C
t
t
t
Reset timing (see
t
t
t
SCL
BUF
HD;STA
SU;STA
SU;STO
HD;DAT
VD;ACK
VD;DAT
SU;DAT
LOW
HIGH
f
r
SP
v(Q)
su(D)
h(D)
w(rst)
rec(rst)
rst
DD
= 2.3 V to 5.5 V; V
t
t
C
A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V
bridge the undefined region SCL’s falling edge.
VD;ACK
VD;DAT
b
= total capacitance of one bus line in pF.
= minimum time for SDA data out to be valid following SCL LOW.
Parameter
SCL clock frequency
bus free time between a
STOP and START
condition
hold time (repeated)
START condition
set-up time for a repeated
START condition
set-up time for STOP
condition
data hold time
data valid acknowledge
time
data valid time
data set-up time
LOW period of the SCL
clock
HIGH period of the SCL
clock
fall time of both SDA and
SCL signals
rise time of both SDA and
SCL signals
pulse width of spikes that
must be suppressed by
the input filter
data output valid time
data input setup time
data input hold time
reset pulse width
reset recovery time
reset time
= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
Dynamic characteristics
L
[1]
100 pF (see
Figure
SS
[6]
[2]
= 0 V; T
21)
Figure 13
amb
= 40 C to +85 C; unless otherwise specified.
Conditions
and
Figure
Rev. 02 — 17 July 2007
[4][5]
12)
Standard mode
Min
300
250
100
4.7
4.0
4.7
4.0
0.3
4.7
4.0
Remote 8-bit I/O expander for Fm+ I
0
0
0
4
4
0
-
-
-
-
I
2
C-bus
1000
3.45
Max
100
300
50
4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
20 + 0.1C
20 + 0.1C
Fast mode I
Min
100
100
1.3
0.6
0.6
0.6
0.1
1.3
0.6
50
0
0
0
4
4
0
-
-
b
b
[3]
[3]
2
C-bus
Max
400
300
300
0.9
50
4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
IL
of the SCL signal) in order to
Fast-mode Plus
0.26
0.26
0.26
0.05
0.26
Min
100
0.5
0.5
50
50
PCA9670
0
0
0
4
4
0
-
-
-
-
© NXP B.V. 2007. All rights reserved.
2
I
C-bus with reset
2
C-bus
1000
Max
0.45
450
120
120
50
4
-
-
-
-
-
-
-
-
-
-
-
-
-
18 of 28
Unit
kHz
ns
ns
ns
ns
ns
ns
s
s
s
s
s
s
s
s
s
s
s
s
s