STM32W108C8U64TR STMicroelectronics, STM32W108C8U64TR Datasheet - Page 90

• Manufacturer Part Number: STM32W108C8U64TR
• Description: 16/32-BITS MICROS
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32W108C8U64TR

• Applications: RF4CE, Remote Control
• Core Processor: ARM® Cortex-M3™
• Program Memory Type: FLASH (64 kB)
• Controller Series: STM32W
• Ram Size: 8K x 8
• Interface: I²C, SPI, UART/USART
• Number Of I /o: 24
• Voltage - Supply: 1.18 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Serial interfaces
9.8.4
90/207
31
15
30
14
Bit 14 INT_SC1PARERR: Parity error received (UART) interrupt enable.
Bit 13 INT_SC1FRMERR: Frame error received (UART) interrupt enable.
Bit 12 INT_SCTXULDB: DMA transmit buffer B unloaded interrupt enable.
Bit 11 INT_SCTXULDA: DMA transmit buffer A unloaded interrupt enable.
Bit 10 INT_SCRXULDB: DMA receive buffer B unloaded interrupt enable.
Serial controller interrupt mode register (SCx_INTMODE)
Address offset: 0xA854 (SC1_INTMODE) and 0xA858 (SC2_INTMODE)
Reset value:
Bit 9 INT_SCRXULDA: DMA receive buffer A unloaded interrupt enable.
Bit 8 INT_SCNAK: NACK received (I
Bit 7 INT_SCCMDFIN: START/STOP command complete (I
Bit 6 INT_SCTXFIN: Transmit operation complete (I
Bit 5 INT_SCRXFIN: Receive operation complete (I
Bit 4 INT_SCTXUND: Transmit buffer underrun interrupt enable.
Bit 3 INT_SCRXOVF: Receive buffer overrun interrupt enable.
Bit 2 INT_SCTXIDLE: Transmitter idle interrupt enable.
Bit 1 INT_SCTXFREE: Transmit buffer free interrupt enable.
Bit 0 INT_SCRXVAL: Receive buffer has data interrupt enable.
Bit 2 SC_TXIDLELEVEL: Transmitter idle interrupt mode
Bit 1 SC_TXFREELEVEL: Transmit buffer free interrupt mode
Bit 0 SC_RXVALLEVEL: Receive buffer has data interrupt mode
29
13
0: Edge triggered
0: Edge triggered
0: Edge triggered
28
12
27
11
0x0000 0000
26
10
Reserved
25
9
Doc ID 018587 Rev 1
24
2
8
C) interrupt enable.
Reserved
23
7
22
2
2
6
C) interrupt enable.
C) interrupt enable.
1: Level triggered.
1: Level triggered.
1: Level triggered.
21
5
2
C) interrupt enable.
20
4
19
3
SC_TX
IDLEL
EVEL
18
rw
2
STM32W108C8
SC_TX
FREEL
EVEL
17
rw
1
SC_RX
VALLE
VEL
16
rw
0