STM32W108C8U64TR STMicroelectronics, STM32W108C8U64TR Datasheet - Page 60

• Manufacturer Part Number: STM32W108C8U64TR
• Description: 16/32-BITS MICROS
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32W108C8U64TR

• Applications: RF4CE, Remote Control
• Core Processor: ARM® Cortex-M3™
• Program Memory Type: FLASH (64 kB)
• Controller Series: STM32W
• Ram Size: 8K x 8
• Interface: I²C, SPI, UART/USART
• Number Of I /o: 24
• Voltage - Supply: 1.18 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

General-purpose input/outputs
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that GPIO activity caused a wake event, but not which specific GPIO was responsible.
Instead, software should read the state of the GPIOs on waking to determine the cause of
the event.
The register GPIO_WAKEFILT contains bits to enable digital filtering of the external wakeup
event sources: the GPIO pins, SC1 activity, SC2 activity, and IRQD. The digital filter
operates by taking samples based on the (nominal) 10 kHz RC oscillator. If three samples in
a row all have the same logic value, and this sampled logic value is different from the logic
value seen upon entering sleep, the filter outputs a wakeup event.
In order to use GPIO pins to wake the STM32W108C8 from deep sleep, the GPIO_WAKE
bit in the WAKE_SEL register must be set. Waking up from GPIO activity does not work with
pins configured for analog mode since the digital logic input is always set to 1 when in
analog mode. Refer to
STM32W108C8's power management and sleep modes.
External interrupts
The STM32W108C8 can use up to four external interrupt sources (IRQA, IRQB, IRQC, and
IRQD), each with its own top level NVIC interrupt vector. Since these external interrupt
sources connect to the standard GPIO input path, an external interrupt pin may
simultaneously be used by a peripheral device or even configured as an output. Analog
mode is the only GPIO configuration that is not compatible with using a pin as an external
interrupt.
External interrupts have individual triggering and filtering options selected using the
registers GPIO_INTCFGA, GPIO_INTCFGB, GPIO_INTCFGC, and GPIO_INTCFGD. The
bit field GPIO_INTMOD of the GPIO_INTCFGx register enables IRQx's second level
interrupt and selects the triggering mode: 0 is disabled; 1 for rising edge; 2 for falling edge; 3
for both edges; 4 for active high level; 5 for active low level. The minimum width needed to
latch an unfiltered external interrupt in both level- and edge-triggered mode is 80 ns. With
the digital filter enabled (the GPIO_INTFILT bit in the GPIO_INTCFGx register is set), the
minimum width needed is 450 ns.
The register INT_GPIOFLAG is the second-level interrupt flag register that indicates
pending external interrupts. Writing 1 to a bit in the INT_GPIOFLAG register clears the flag
while writing 0 has no effect. If the interrupt is level-triggered, the flag bit is set again
immediately after being cleared if its input is still in the active state.
Two of the four external interrupts, IRQA and IRQB, have fixed pin assignments. The other
two external interrupts, IRQC and IRQD, can use any GPIO pin. The GPIO_IRQCSEL and
GPIO_IRQDSEL registers specify the GPIO pins assigned to IRQC and IRQD, respectively.
Table 9
GPIO pin used for the external interrupt.
Table 9.
GPIO_IRQxSEL
shows how the GPIO_IRQCSEL and GPIO_IRQDSEL register values select the
0
1
2
3
IRQC/D GPIO selection
GPIO
PA0
PA1
PA2
PA3
Section 6: System modules on page 32
Doc ID 018587 Rev 1
GPIO_IRQxSEL
10
11
8
9
GPIO
PB0
PB1
PB2
PB3
GPIO_IRQxSEL
for information on the
16
17
18
19
STM32W108C8
GPIO
PC0
PC1
PC2
PC3