STM32W108C8U64TR STMicroelectronics, STM32W108C8U64TR Datasheet - Page 176

• Manufacturer Part Number: STM32W108C8U64TR
• Description: 16/32-BITS MICROS
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32W108C8U64TR

• Applications: RF4CE, Remote Control
• Core Processor: ARM® Cortex-M3™
• Program Memory Type: FLASH (64 kB)
• Controller Series: STM32W
• Ram Size: 8K x 8
• Interface: I²C, SPI, UART/USART
• Number Of I /o: 24
• Voltage - Supply: 1.18 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Interrupts
12.3.2
12.3.3
176/207
INT_I
RQD
31
15
rw
31
INT_I
RQC
30
14
rw
30
Top-level clear interrupts configuration register (INT_CFGCLR)
Address offset: 0x0180
Reset value:
Top-level set interrupts pending register (INT_PENDSET)
Address offset: 0x0200
Reset value:
Bit 16 INT_DEBUG: Write 1 to disable debug interrupt. (Writing 0 has no effect.)
Bit 15 INT_IRQD: Write 1 to disable IRQD interrupt. (Writing 0 has no effect.)
Bit 14 INT_IRQC: Write 1 to disable IRQC interrupt. (Writing 0 has no effect.)
Bit 13 INT_IRQB: Write 1 to disable IRQB interrupt. (Writing 0 has no effect.)
Bit 12 INT_IRQA: Write 1 to disable IRQA interrupt. (Writing 0 has no effect.)
Bit 11 INT_ADC: Write 1 to disable ADC interrupt. (Writing 0 has no effect.)
Bit 10 INT_MACRX: Write 1 to disable MAC receive interrupt. (Writing 0 has no effect.)
INT_I
Bit 9 INT_MACTX: Write 1 to disable MAC transmit interrupt. (Writing 0 has no effect.)
Bit 8 INT_MACTMR: Write 1 to disable MAC timer interrupt. (Writing 0 has no effect.)
Bit 7 INT_SEC: Write 1 to disable security interrupt. (Writing 0 has no effect.)
Bit 6 INT_SC2: Write 1 to disable serial controller 2 interrupt. (Writing 0 has no effect.)
Bit 5 INT_SC1: Write 1 to disable serial controller 1 interrupt. (Writing 0 has no effect.)
Bit 4 INT_SLEEPTMR: Write 1 to disable sleep timer interrupt. (Writing 0 has no effect.)
Bit 3 INT_BB: Write 1 to disable baseband interrupt. (Writing 0 has no effect.)
Bit 2 INT_MGMT: Write 1 to disable management interrupt. (Writing 0 has no effect.)
Bit 1 INT_TIM2: Write 1 to disable timer 2 interrupt. (Writing 0 has no effect.)
Bit 0 INT_TIM1: Write 1 to disable timer 1 interrupt. (Writing 0 has no effect.)
RQB
29
13
rw
29
INT_I
RQA
28
12
28
rw
INT_A
DC
27
11
27
rw
0x0000 0000
0x0000 0000
INT_M
ACRX
26
10
26
rw
INT_M
ACTX
25
25
rw
9
Doc ID 018587 Rev 1
Reserved
Reserved
INT_M
ACTM
24
24
rw
R
8
INT_S
EC
23
rw
23
7
INT_S
C2
22
22
rw
6
INT_SC
21
rw
21
5
1
INT_S
LEEP
TMR
20
rw
20
4
INT_B
19
rw
19
3
B
INT_M
GMT
18
18
rw
2
STM32W108C8
INT_TI
M2
17
17
rw
1
INT_TI
INT_D
EBUG
INT_D
EBUG
M1
16
rw
rw
16
rw
0