Si5369-EVB Silicon Laboratories Inc, Si5369-EVB Datasheet - Page 80

• Manufacturer Part Number: Si5369-EVB
• Description: MCU, MPU & DSP Development Tools SI5369 DEV KIT
• Manufacturer: Silicon Laboratories Inc

Specifications of Si5369-EVB

• Processor To Be Evaluated: Si5369
• Interface Type: I2C, SPI
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: Details

80
Notes:
General
Solder Mask Design
Stencil Design
Card Assembly
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
9. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center
10. A No-Clean, Type-3 solder paste is recommended.
11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for
(LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
mask and the metal pad is to be 60 µm minimum, all the way around the pad.
used to assure good solder paste release.
ground pad.
Small Body Components.
Dimension
GE
GD
ZD
E2
D2
ZE
R1
R2
E
D
X
Y
e
Table 12. PCB Land Pattern Dimensions
Preliminary Rev. 0.4
13.90
13.90
3.90
3.90
MIN
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—
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15.40 REF.
15.40 REF.
0.50 BSC.
1.50 REF.
0.15 REF
16.90
16.90
MAX
4.10
4.10
0.30
1.00
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