Si5369-EVB Silicon Laboratories Inc, Si5369-EVB Datasheet - Page 30

MCU, MPU & DSP Development Tools SI5369 DEV KIT

Si5369-EVB

Manufacturer Part Number
Si5369-EVB
Description
MCU, MPU & DSP Development Tools SI5369 DEV KIT
Manufacturer
Silicon Laboratories Inc
Datasheets

Specifications of Si5369-EVB

Processor To Be Evaluated
Si5369
Interface Type
I2C, SPI
Operating Supply Voltage
3.3 V
Lead Free Status / Rohs Status
 Details
Reset value = 0010 1010
30
Register 7.
Name
Type
7:6
5:3
2:0
Bit
Bit
SFOUT5_REG [2:0]
FOSREFSEL [2:0]
D7
Reserved.
Reserved
Name
R
D6
SFOUT5_REG [2:0]
Controls output signal format and disable for CKOUT5 output buffer. The
LVPECL and CMOS output formats draw more current than either LVDS or CML;
however, there are restrictions in the allowed output format pin settings so that
the maximum power dissipation for the TQFP devices is limited when they are
operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs, the
fifth output must be disabled. When there are five enabled outputs, there can be
no more than three outputs that are either LVPECL or CMOS.
000: Reserved
001: Disable
010: CMOS
011: Low swing LVDS
100: Reserved
101: LVPECL
110: CML
111: LVDS
FOSREFSEL [2:0].
Selects which input clock is used as the reference frequency for Frequency Off-
Set (FOS) alarms.
000: XA/XB (External reference)
001: CKIN1
010: CKIN2
011: CKIN3
100: CKIN4
101: Reserved
110: Reserved
111: Reserved
D5
SFOUT5_REG [2:0]
Preliminary Rev. 0.4
R/W
D4
D3
Function
D2
FOSREFSEL [2:0]
R/W
D1
D0

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