IDT82P2282PFG8 IDT, Integrated Device Technology Inc, IDT82P2282PFG8 Datasheet - Page 30
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IDT82P2282PFG8
Manufacturer Part Number
IDT82P2282PFG8
Description
TXRX T1/J1/E1 2CHAN 100-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Transceiverr
Datasheet
1.IDT82P2282PF8.pdf
(381 pages)
Specifications of IDT82P2282PFG8
Number Of Drivers/receivers
2/2
Protocol
IEEE 1149.1
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Screening Level
Industrial
Pin Count
100
Mounting
Surface Mount
Package Type
TQFP
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
82P2282PFG8
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Part Number:
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Manufacturer:
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IDT82P2282
3.7
3.7.1
3.7.1.1
selection is made by the R_MD bit.
3.7.1.2
selection is made by the R_MD bit.
3.7.2
3.7.2.1
the BPV error will be detected if two consecutive pulses are received
with the same polarity (refer to Figure 8). The event of the Bipolar Viola-
tion (BPV) Error is forwarded to the Performance Monitor.
used, a CV error is detected when the received code does not match the
standard B8ZS line code pattern (expect the Excessive Zero error).
AMI and B8ZS line code rules. There are two standards defining the
EXZ error: ANSI and FCC. The EXZ_DEF bit chooses a standard for the
corresponding link to judge the EXZ error. Table 8 shows the definition of
EXZ. To count the event of the Excessive Zero (EXZ) Error, the
EXZ_ERR[1:0] bits should be set to ‘01’. The Excessive Zero (EXZ)
Error is counted in an internal 16-bit EXZ counter. The content in the
EXZ counter is transferred to the EXZ Error Counter L-Byte & H-Byte
registers in two ways:
selected. The EXZ counter transfers its content to the EXZ Error
Counter L-Byte & H-Byte registers when there is a transition from ‘0’ to
‘1’ on the CNT_TRF bit;
The EXZ counter transfers its content to the EXZ Error Counter L-Byte &
H-Byte registers every one second automatically.
Counter L-Byte & H-Byte registers, the counter will be cleared to ‘0’ and
start a new round counting automatically. No error event is lost during
data transferring.
can trigger an interrupt if the corresponding CNT_IE bit is set.
(CV) Error is detected, it will be indicated by the CV_IS bit. When the
Excessive Zero (EXZ) Error is detected, it will be indicated by the
EXZ_IS bit. When the CV_IS bit or the EXZ_IS bit is ‘1’, an interrupt will
be reported by the INT pin if enabled by the corresponding CV_IE bit or
the EXZ_IE bit.
Functional Description
In T1/J1 mode, the AMI and B8ZS line code rules are provided. The
In E1 mode, the AMI and HDB3 line code rules are provided. The
The decode errors can be divided into three types in T1/J1 mode:
1. Bipolar Violation (BPV) Error: When AMI line code rule is used,
2. B8ZS Code Violation (CV) Error: When B8ZS line code rule is
3. Excessive Zero (EXZ) Error: EXZ error can be detected in both
a. When the CNT_MD bit is ‘0’, the Manual-Report mode is
b. When the CNT_MD bit is ‘1’, the Auto-Report mode is selected.
After the content in the counter is transferred to the EXZ Error
The overflow of the counter is reflected by the CNTOV_IS bit, and
When the Bipolar Violation (BPV) Error or the B8ZS Code Violation
DECODER
LINE CODE RULE
DECODE ERROR DETECTION
T1 / J1 Mode
E1 Mode
T1 / J1 Mode
30
3.7.2.2
the BPV error will be detected if two consecutive pulses are received
with the same polarity (refer to Figure 8). The event of the Bipolar Viola-
tion (BPV) Error is forwarded to the Performance Monitor.
used, a CV error is detected if two consecutive BPV errors are detected,
and the pulses that have the same polarity as the previous pulse are not
the HDB3 zero substitution pulsed (refer to Figure 10).
AMI and HDB3 line code rules. There are two standards defining the
EXZ error: ANSI and FCC. The EXZ_DEF bit chooses a standard for the
corresponding link to judge the EXZ error. Table 8 shows the definition of
EXZ. To count the event of the Excessive Zero (EXZ) Error, the
EXZ_ERR[1:0] bits should be set to ‘01’. The Excessive Zero (EXZ)
Error is counted in an internal 16-bit EXZ counter. The content in the
EXZ counter is transferred to the EXZ Error Counter L-Byte & H-Byte
registers in two ways:
selected. The EXZ counter transfers its content to the EXZ Error
Counter L-Byte & H-Byte registers when there is a transition from ‘0’ to
‘1’ on the CNT_TRF bit;
The EXZ counter transfers its content to the EXZ Error Counter L-Byte &
H-Byte registers every one second automatically.
Counter L-Byte & H-Byte registers, the counter will be cleared to ‘0’ and
start a new round counting automatically. No error event is lost during
data transferring.
can trigger an interrupt if the corresponding CNT_IE bit is set.
(CV) Error is detected, it will be indicated by the CV_IS bit. When the
Excessive Zero (EXZ) Error is detected, it will be indicated by the
EXZ_IS bit. When the CV_IS bit or the EXZ_IS bit is ‘1’, an interrupt will
be reported by the INT pin if enabled by the corresponding CV_IE bit or
the EXZ_IE bit.
Table 8: Excessive Zero Error Definition
HDB3
B8ZS
AMI
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
The decode errors can be divided into three types in E1 mode:
1. Bipolar Violation (BPV) Error: When AMI line code rule is used,
2. HDB3 Code Violation (CV) Error: When HDB3 line code rule is
3. Excessive Zero (EXZ) Error: EXZ error can be detected in both
a. When the CNT_MD bit is ‘0’, the Manual-Report mode is
b. When the CNT_MD bit is ‘1’, the Auto-Report mode is selected.
After the content in the counter is transferred to the EXZ Error
The overflow of the counter is reflected by the CNTOV_IS bit, and
When the Bipolar Violation (BPV) Error or the HDB3 Code Violation
More than 15 consecutive 0s are
detected.
More than 7 consecutive 0s are
detected (refer to Figure 9).
More than 3 consecutive 0s are
detected (refer to Figure 10).
E1 Mode
ANSI
More than 80 consecutive 0s are
detected.
More than 7 consecutive 0s are
detected (refer to Figure 9).
More than 3 consecutive 0s are
detected (refer to Figure 10).
August 20, 2009
FCC
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