IDT82P2282PFG8 IDT, Integrated Device Technology Inc, IDT82P2282PFG8 Datasheet - Page 20
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IDT82P2282PFG8
Manufacturer Part Number
IDT82P2282PFG8
Description
TXRX T1/J1/E1 2CHAN 100-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Transceiverr
Datasheet
1.IDT82P2282PF8.pdf
(381 pages)
Specifications of IDT82P2282PFG8
Number Of Drivers/receivers
2/2
Protocol
IEEE 1149.1
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Screening Level
Industrial
Pin Count
100
Mounting
Surface Mount
Package Type
TQFP
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
82P2282PFG8
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT82P2282PFG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
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IDT82P2282
Pin Description
GNDDIO[0]
GNDDIO[1]
GNDDIO[2]
VDDDIO[0]
VDDDIO[1]
VDDDIO[2]
GNDDC[0]
GNDDC[1]
GNDDC[2]
GNDDC[3]
VDDDC[0]
VDDDC[1]
VDDDC[2]
VDDDC[3]
GNDAR[1]
GNDAR[2]
GNDAX[1]
GNDAX[2]
VDDAR[1]
VDDAR[2]
GNDAT[1]
GNDAT[2]
VDDAX[1]
VDDAX[2]
VDDAT[1]
VDDAT[2]
GNDAP
GNDAB
VDDAP
VDDAB
Name
TMS
TDO
TCK
TDI
Ground
Ground
Ground
Ground
Ground
Ground
Ground
High-Z
Power
Power
Power
Power
Power
Power
Power
Type
Input
Input
Input
Pin No.
100
98
99
96
93
40
64
89
44
59
91
42
61
88
45
58
26
13
29
10
25
14
24
15
20
19
23
16
3
4
6
5
8
7
TMS: Test Mode Select
The signal on this pin controls the JTAG test performance and is sampled on the rising edge of TCK. This pin is a
Schmitt-triggered input with an internal pull-up resistor.
TCK: Test Clock
The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge of TCK and TDO is
clocked out of the device on the falling edge of TCK. This pin is a Schmitt-triggered input with an internal pull-up resis-
tor.
TDI: Test Input
The test data is sampled at this pin on the rising edge of TCK. This pin has an internal pull-up resistor. This pin is a
Schmitt-triggered input with an internal pull-up resistor.
TDO: Test Output
The test data are output on this pin. It is updated on the falling edge of TCK. This pin is High-Z except during the pro-
cess of data scanning.
VDDDIO[2:0]: 3.3 V I/O Power Supply
GNDDIO[2:0]: Digital Pad Ground
VDDDC[3:0]: 1.8 V Digital Core Power Supply
GNDDC[3:0]: Digital Core Ground
VDDAR[2:1]: 3.3 V Power Supply for Receiver
GNDAR[2:1]: Analog Ground for Receiver
VDDAT[2:1]: 3.3 V Power Supply for Transmitter
GNDAT[2:1]: Analog Ground for Transmitter
VDDAX[2:1]: 3.3 V Power Supply for Transmit Driver
GNDAX[2:1]: Analog Ground for Transmitter Driver
VDDAP: 3.3 V Power Analog PLL
GNDAP: Analog Ground PLL
VDDAB: 3.3 V Power Analog Bias
GNDAB: Analog Ground Bias
Power & Ground
TEST
20
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Description
August 20, 2009
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