IDT82P2282PFG8 IDT, Integrated Device Technology Inc, IDT82P2282PFG8 Datasheet - Page 273
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IDT82P2282PFG8
Manufacturer Part Number
IDT82P2282PFG8
Description
TXRX T1/J1/E1 2CHAN 100-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Transceiverr
Datasheet
1.IDT82P2282PF8.pdf
(381 pages)
Specifications of IDT82P2282PFG8
Number Of Drivers/receivers
2/2
Protocol
IEEE 1149.1
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Screening Level
Industrial
Pin Count
100
Mounting
Surface Mount
Package Type
TQFP
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
82P2282PFG8
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT82P2282PFG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
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E1 RBIF Option Register (046H, 146H)
DE:
and MRSIG.
FE:
CMS:
bit of the two links should be set to the same value.
TRI:
Programming Information
IDT82P2282
Bit Name
Default
Bit No.
Type
This bit selects the active edge of RSCKn to update the data on RSDn and RSIGn and the active edge of MRSCK to update the data on MRSD
= 0: The falling edge is selected.
= 1: The rising edge is selected.
In Receive Multiplexed mode, the bit of the two links should be set to the same value.
This bit selects the active edge of RSCKn to update/sample the pulse on RSFSn and the active edge of MRSCK to sample the pulse on MRSFS.
= 0: The falling edge is selected.
= 1: The rising edge is selected.
In Receive Multiplexed mode, the bit of the two links should be set to the same value.
This bit is valid in Receive Clock Slave mode and Receive Multiplexed mode.
= 0: The speed of RSCKn/MRSCK is the same as the data rate on the system side (2.048 Mb/s / 8.192 Mb/s).
= 1: The speed of RSCKn/MRSCK is double the data rate on the system side (4.096 Mb/s / 16.384 Mb/s).
In Receive Clock Slave mode, if both two links use the RSCK[1] and RSFS[1] to output the data (i.e., the RSLVCK bit (b, E1-01H) is set to ‘1’), the
In Receive Multiplexed mode, the bit of the two links should be set to the same value.
= 0: The processed data and signaling bits are output on the RSDn/MRSD and RSIGn/MRSIG pins respectively.
= 1: The output on the RSDn/MRSD and RSIGn/MRSIG pins are in high impedance.
7
6
Reserved
5
4
273
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
R/W
DE
3
1
R/W
FE
2
1
CMS
R/W
1
0
August 20, 2009
R/W
TRI
0
1
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