IDT82P2282PFG8 IDT, Integrated Device Technology Inc, IDT82P2282PFG8 Datasheet - Page 10
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IDT82P2282PFG8
Manufacturer Part Number
IDT82P2282PFG8
Description
TXRX T1/J1/E1 2CHAN 100-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Transceiverr
Datasheet
1.IDT82P2282PF8.pdf
(381 pages)
Specifications of IDT82P2282PFG8
Number Of Drivers/receivers
2/2
Protocol
IEEE 1149.1
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Screening Level
Industrial
Pin Count
100
Mounting
Surface Mount
Package Type
TQFP
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
82P2282PFG8
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT82P2282PFG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
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List of Figures
Figure 1. 100-Pin TQFP (Top View) ............................................................................................................................................................................ 14
Figure 2. Receive / Transmit Line Circuit .................................................................................................................................................................... 25
Figure 3. Receive Path Monitoring (Twisted Pair) ....................................................................................................................................................... 26
Figure 4. Transmit Path Monitoring (Twisted Pair) ...................................................................................................................................................... 26
Figure 5. Receive Path Monitoring (COAX) ................................................................................................................................................................ 27
Figure 6. Transmit Path Monitoring(COAX) ................................................................................................................................................................ 27
Figure 7. Jitter Attenuator ............................................................................................................................................................................................ 29
Figure 8. AMI Bipolar Violation Error ........................................................................................................................................................................... 31
Figure 9. B8ZS Excessive Zero Error ......................................................................................................................................................................... 31
Figure 10. HDB3 Code Violation & Excessive Zero Error ............................................................................................................................................ 31
Figure 11. E1 Frame Searching Process ..................................................................................................................................................................... 42
Figure 12. Basic Frame Searching Process ................................................................................................................................................................ 43
Figure 13. TS16 Structure Of CAS Signaling Multi-Frame .......................................................................................................................................... 45
Figure 14. Standard HDLC Packet .............................................................................................................................................................................. 56
Figure 15. Overhead Indication In The FIFO ............................................................................................................................................................... 57
Figure 16. Signaling Output In T1/J1 Mode ................................................................................................................................................................. 61
Figure 17. Signaling Output In E1 Mode ...................................................................................................................................................................... 61
Figure 18. T1/J1 To E1 Format Mapping - G.802 Mode .............................................................................................................................................. 66
Figure 19. T1/J1 To E1 Format Mapping - One Filler Every Fourth Channel Mode .................................................................................................... 66
Figure 20. T1/J1 To E1 Format Mapping - Continuous Channels Mode ..................................................................................................................... 67
Figure 21. No Offset When FE = 1 & DE = 1 In Receive Path .................................................................................................................................... 68
Figure 22. No Offset When FE = 0 & DE = 0 In Receive Path .................................................................................................................................... 68
Figure 23. No Offset When FE = 0 & DE = 1 In Receive Path .................................................................................................................................... 69
Figure 24. No Offset When FE = 1 & DE = 0 In Receive Path .................................................................................................................................... 69
Figure 25. E1 To T1/J1 Format Mapping - G.802 Mode .............................................................................................................................................. 74
Figure 26. E1 To T1/J1 Format Mapping - One Filler Every Fourth Channel Mode .................................................................................................... 74
Figure 27. E1 To T1/J1 Format Mapping - Continuous Channels Mode ..................................................................................................................... 75
Figure 28. No Offset When FE = 1 & DE = 1 In Transmit Path ................................................................................................................................... 76
Figure 29. No Offset When FE = 0 & DE = 0 In Transmit Path ................................................................................................................................... 76
Figure 30. No Offset When FE = 0 & DE = 1 In Transmit Path ................................................................................................................................... 77
Figure 31. No Offset When FE = 1 & DE = 0 In Transmit Path ................................................................................................................................... 77
Figure 32. DSX-1 Waveform Template ........................................................................................................................................................................ 93
Figure 33. T1/J1 Pulse Template Measurement Circuit .............................................................................................................................................. 93
Figure 34. E1 Waveform Template .............................................................................................................................................................................. 93
Figure 35. E1 Pulse Template Measurement Circuit ................................................................................................................................................... 93
Figure 36. G.772 Non-Intrusive Monitor .................................................................................................................................................................... 105
Figure 37. Hardware Reset When Powered-Up ........................................................................................................................................................ 108
Figure 38. Hardware Reset In Normal Operation ...................................................................................................................................................... 108
Figure 39. Read Operation In SPI Mode ................................................................................................................................................................... 109
Figure 40. Write Operation In SPI Mode .................................................................................................................................................................... 109
Figure 41. JTAG Architecture .................................................................................................................................................................................... 357
Figure 42. JTAG State Diagram ................................................................................................................................................................................ 363
Figure 43. I/O Timing in Non-Multiplexed Mode ........................................................................................................................................................ 366
Figure 44. I/O Timing in Multiplexed Mode ................................................................................................................................................................ 367
Figure 45. T1/J1 Jitter Tolerance Performance Requirement .................................................................................................................................... 372
Figure 46. E1 Jitter Tolerance Performance Requirement ........................................................................................................................................ 373
Figure 47. T1/J1 Jitter Transfer Performance Requirement (AT&T62411 / GR-253-CORE / TR-TSY-000009) ....................................................... 374
Figure 48. E1 Jitter Transfer Performance Requirement (G.736) .............................................................................................................................. 375
List of Figures
10
August 20, 2009
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