IDT82P2282PFG8 IDT, Integrated Device Technology Inc, IDT82P2282PFG8 Datasheet - Page 203
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IDT82P2282PFG8
Manufacturer Part Number
IDT82P2282PFG8
Description
TXRX T1/J1/E1 2CHAN 100-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Transceiverr
Datasheet
1.IDT82P2282PF8.pdf
(381 pages)
Specifications of IDT82P2282PFG8
Number Of Drivers/receivers
2/2
Protocol
IEEE 1149.1
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Screening Level
Industrial
Pin Count
100
Mounting
Surface Mount
Package Type
TQFP
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
82P2282PFG8
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT82P2282PFG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
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T1/J1 THDLC1 Control (0A7H, 1A7H)
T1/J1 THDLC2 Control (0A8H, 1A8H)
T1/J1 THDLC3 Control (0A9H, 1A9H)
EOM:
ABORT:
THDLCM:
TRST:
Programming Information
IDT82P2282
Bit Name
Bit Name
Bit Name
Default
Default
Default
Bit No.
Bit No.
Bit No.
Type
Type
Type
The function of the above three sets of registers are the same. However, they correspond to different THDLC.
A transition from ‘0’ to ‘1’ on this bit indicates an entire HDLC packet is stored in the FIFO and starts the packet transmission.
= 0: Disable the manual abort sequence insertion.
= 1: The abort sequence (‘01111111’) is manually inserted to the current HDLC packet.
This bit is self-cleared after the abortion.
= 0: HDLC mode is selected.
= 1: Reserved.
A transition from ‘0’ to ‘1’ on the this bit resets the corresponding HDLC Transmitter. The reset will clear the FIFO.
7
7
7
Reserved
Reserved
Reserved
6
6
6
5
5
5
EOM
EOM
EOM
R/W
R/W
R/W
4
0
4
0
4
0
203
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Reserved
Reserved
Reserved
3
3
3
ABORT
ABORT
ABORT
R/W
R/W
R/W
2
0
2
0
2
0
THDLCM
THDLCM
THDLCM
R/W
R/W
R/W
1
0
1
0
1
0
August 20, 2009
TRST
TRST
TRST
R/W
R/W
R/W
0
0
0
0
0
0
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