IDT82P2282PFG8 IDT, Integrated Device Technology Inc, IDT82P2282PFG8 Datasheet - Page 274
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IDT82P2282PFG8
Manufacturer Part Number
IDT82P2282PFG8
Description
TXRX T1/J1/E1 2CHAN 100-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Transceiverr
Datasheet
1.IDT82P2282PF8.pdf
(381 pages)
Specifications of IDT82P2282PFG8
Number Of Drivers/receivers
2/2
Protocol
IEEE 1149.1
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Screening Level
Industrial
Pin Count
100
Mounting
Surface Mount
Package Type
TQFP
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
82P2282PFG8
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT82P2282PFG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
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E1 RBIF Mode (047H, 147H)
RMODE:
align the data output on the RSDn pin are received from each line side.
align the data output on the RSDn pin are provided by the system side.
E1 RBIF Frame Pulse (048H, 148H)
FSINV:
OHD, SMFS, CMFS:
Programming Information
IDT82P2282
Bit Name
Bit Name
Default
Default
Bit No.
Bit No.
Type
Type
In Receive Non-multiplexed mode, this bit selects the sub-mode.
= 0: The Receive System Interface is operated in Receive Clock Master mode. The timing signal for clocking the data and the framing pulse to
= 1: The Receive System Interface is operated in Receive Clock Slave mode. The timing signal for clocking the data and the framing pulse to
= 0: The receive framing pulse RSFSn is active high.
= 1: The receive framing pulse RSFSn is active low.
In Receive Multiplexed mode, this bit of the two links should be set to the same value.
In Receive Clock Master mode, these bits select what the pulse on RSFSn indicates.
OHD
0
0
0
0
1
SMFS
0
0
1
1
0
7
7
CMFS
0
1
0
1
0
Reserved
6
6
The RSFSn pulses during the first bit of each Basic frame.
The RSFSn pulses during the first bit of each CRC Multi-frame.
The RSFSn pulses during the first bit of each Signaling Multi-frame.
The RSFSn goes high/low during the first bit of each Signaling Multi-frame and goes the opposite during the sec-
ond bit of each CRC Multi-frame.
The RSFSn pulses during the TS0 and TS16.
5
5
Reserved
FSINV
R/W
4
4
0
274
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
RSFSn Indication
OHD
R/W
3
3
0
SMFS
R/W
2
2
0
CMFS
R/W
1
1
0
August 20, 2009
Reserved
RMODE
R/W
0
1
0
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