ICS1893AF IDT, Integrated Device Technology Inc, ICS1893AF Datasheet - Page 89

• Manufacturer Part Number: ICS1893AF
• Description: PHYCEIVER LOW PWR 3.3V 48-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893AF

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Other names: 1893AF

8.12.3 Auto-Negotiation Progress Monitor (bits 17.13:11)
8.12.4 100Base-TX Receive Signal Lost (bit 17.10)
ICS1893AF, Rev. D 10/26/04
The Auto-Negotiation Progress Monitor consists of the Auto-Negotiation Complete bit (bit 17.4) and the
three Auto-Negotiation Monitor bits (bits 17.13:11). The Auto-Negotiation Progress Monitor continually
examines the state of the Auto-Negotiation Process State Machine and reports the status of
Auto-Negotiation using the three Auto-Negotiation Monitor bits. Therefore, the value of these three bits
provides the status of the Auto-Negotiation Process.
These three bits are initialized to logic zero in one of the following ways:
•
•
•
If Auto-Negotiation is enabled, these bits continually latch the highest state that the Auto-Negotiation State
Machine achieves. That is, they are updated only if the binary value of the next state is greater than the
binary value of the present state as outlined in
Note:
Table 8-19. Auto-Negotiation State Machine (Progress Monitor)
The 100Base-TX Receive Signal Lost bit indicates to an STA whether the ICS1893AF has lost its
100Base-TX Receive Signal. If this bit is set to a logic:
•
•
This bit is a latching high bit. (For more information on latching high and latching low bits, see
8.1.4.1, “Latching High Bits”
Note:
Auto-Negotiation State Machine
Idle
Parallel Detected
Parallel Detection Failure
Ability Matched
Acknowledge Match Failure
Acknowledge Matched
Consistency Match Failure
Consistency Matched
Auto-Negotiation Completed
Successfully
A reset (see
Disabling Auto-Negotiation [see
Restarting Auto-Negotiation [see
Zero, it indicates the Receive Signal has remained valid since either the last read or reset of this register.
One, it indicates the Receive Signal was lost since either the last read or reset of this register.
ICS1893AF Data Sheet - Release
An MDIO read of these bits provides a history of the greatest progress achieved by the
auto-negotiation process. In addition, the MDIO read latches the present state of the
Auto-Negotiation State Machine for a subsequent read.
This bit has no definition in 10Base-T mode.
Section 5.1, “Reset
and
Copyright © 2004, Integrated Circuit Systems, Inc.
Section 8.1.4.2, “Latching Low
Section 8.2.4, “Auto-Negotiation Enable (bit
Operations”)
Section 8.2.7, “Restart Auto-Negotiation (bit
Complete Bit
Negotiation
(Bit 17.4)
Auto-
All rights reserved.
0
0
0
0
0
0
0
0
1
Table
89
Auto-Negotiation Progress Monitor
8-19.
Monitor Bit 2
Negotiation
(Bit 17.13)
Auto-
0
0
0
0
1
1
1
1
0
Bits”.)
Monitor Bit 1
Chapter 8 Management Register Set
Negotiation
(Bit 17.12)
Auto-
0
0
1
1
0
0
1
1
0
0.12)”]
0.9)”]
Monitor Bit 0
Negotiation
(Bit 17.11)
Auto-
0
1
0
1
0
1
0
1
0
October, 2004
Section