ICS1893AF IDT, Integrated Device Technology Inc, ICS1893AF Datasheet
ICS1893AF
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ICS1893AF Summary of contents
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... Integrated Circuit Systems, Inc. 3.3-V 10Base-T/100Base-TX Integrated PHYceiver General The ICS1893AF is a lower cost, re-packaged version of the ICS1893Y-10. The ICS1893AF is a fully integrated, Physical Layer device (PHY) that is compliant with both the 10Base-T and 100Base-TX CSMA/CD Ethernet Standard, ISO/IEC 8802-3. The ICS1893AF uses the same proven silicon as the ICS1893Y-10 but offers a lower cost solution by using a lower cost 300 mil ...
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... Revision History ............................................................................................................................. 9 Chapter 1 Abbreviations and Acronyms ......................................................................................... 10 Chapter 2 Conventions and Nomenclature..................................................................................... 12 Chapter 3 Typical ICS1893AF Applications..................................................................................... 14 3.1 ICS1893AF / ICS1893Y-10 Pin Differences ...........................................................14 3.2 ICS1893AF / ICS1893Y-10 Shared Features .........................................................15 Chapter 4 Overview of the ICS1893AF............................................................................................. 16 4.1 100Base-TX Operation ..........................................................................................17 4.2 10Base-T Operation ...............................................................................................17 Chapter 5 Operating Modes Overview............................................................................................. 18 5.1 Reset Operations ...................................................................................................19 5 ...
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... ICS1893AF Data Sheet - Release Section 7.3 Functional Block: 100Base-X PCS and PMA Sublayers ........................................40 7.3.1 PCS Sublayer ........................................................................................................40 7.3.2 PMA Sublayer ........................................................................................................40 7.3.3 PCS/PMA Transmit Modules .................................................................................41 7.3.4 PCS/PMA Receive Modules ..................................................................................42 7.3.5 PCS Control Signal Generation .............................................................................43 7.3.6 4B/5B Encoding/Decoding .....................................................................................43 7.4 Functional Block: 100Base-TX TP-PMD Operations .............................................44 7 ...
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... ICS1893AF Data Sheet - Release Section Chapter 8 Management Register Set ............................................................................................... 55 8.1 Introduction to Management Register Set .............................................................56 8.1.1 Management Register Set Outline .........................................................................56 8.1.2 Management Register Bit Access ..........................................................................57 8.1.3 Management Register Bit Default Values ..............................................................57 8.1.4 Management Register Bit Special Functions .........................................................58 8.2 Register 0: Control Register ...................................................................................59 8.2.1 Reset (bit 0 ...
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... ICS1893AF Data Sheet - Release Section 8.5 Register 3: PHY Identifier Register ........................................................................70 8.5.1 OUI bits 19-24 (bits 3.15:10) ..................................................................................70 8.5.2 Manufacturer’s Model Number (bits 3.9:4) .............................................................71 8.5.3 Revision Number (bits 3.3:0) .................................................................................71 8.6 Register 4: Auto-Negotiation Register ...................................................................72 8.6.1 Next Page (bit 4.15) ...............................................................................................72 8.6.2 IEEE Reserved Bit (bit 4.14) ..................................................................................72 8 ...
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... ICS1893AF Data Sheet - Release Section 8.11 Register 16: Extended Control Register ................................................................84 8.11.1 Command Override Write Enable (bit 16.15) .........................................................85 8.11.2 ICS Reserved (bits 16.14:11) .................................................................................85 8.11.3 PHY Address (bits 16.10:6) ...................................................................................85 8.11.4 Stream Cipher Scrambler Test Mode (bit 16.5) .....................................................85 8.11.5 ICS Reserved (bit 16.4) .........................................................................................85 8.11.6 NRZ/NRZI Encoding (bit 16 ...
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... ICS1893AF Data Sheet - Release Section 8.14 Register 19: Extended Control Register 2 .............................................................96 8.14.1 Node/Repeater Configuration (bit 19.15) ...............................................................97 8.14.2 Hardware/Software Priority Status (bit 19.14) ........................................................97 8.14.3 Remote Fault (bit 19.13) ........................................................................................97 8.14.4 ICS Reserved (bits 19.12:8) ...................................................................................97 8.14.5 Twisted Pair Tri-State Enable, TPTRI (bit 19.7) .....................................................97 8.14.6 ICS Reserved (bits 19 ...
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... Jabber Timing .....................................................................................131 10.5.19 10Base-T: Normal Link Pulse Timing ..................................................................132 10.5.20 Auto-Negotiation Fast Link Pulse Timing .............................................................133 Chapter 11 Physical Dimensions of ICS1893AF Package ........................................................... 134 Chapter 12 Ordering Information ................................................................................................... 135 ICS1893AF, Rev D 10/26/04 Table of Contents Title Copyright © 2004, Integrated Circuit Systems, Inc. ...
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... Figure 12-1, “Odering Information” added part number ICS1893AFLF = 48 Lead 300 mil. SSOP Lead Free Commercial Temperature package and part number ICS1893AFILF = 48 Lead 300 mil. SSOP Lead Free Industrial Temperature package. ICS1893AF, Rev. D 10/26/04 Copyright © 2004, Integrated Circuit Systems, Inc. ...
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... ICS1893AF Data Sheet - Release Chapter 1 Abbreviations and Acronyms Table 1-1 lists and interprets the abbreviations and acronyms used throughout this data sheet. Table 1-1. Abbreviations and Acronyms Abbreviation / Acronym 4B/5B 4-Bit / 5-Bit Encoding/Decoding ANSI American National Standards Institute CMOS complimentary metal-oxide semiconductor ...
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... Open Systems Interconnection OUI Organizationally Unique Identifier PCS Physical Coding sublayer PHY physical-layer device The ICS1893AF is a physical-layer device, also referred ‘PHY’ or ‘PHYceiver’. (The ICS1890 is also a physical-layer device.) PLL phase-locked loop PMA Physical Medium Attachment PMD Physical Medium Dependent ...
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... All pin or signal names are provided in capital letters. • A pin name that includes a forward slash ‘/’ multi-function, configuration pin. These pins provide the ability to select between two ICS1893AF functions. The name provided: – Before the ‘/’ indicates the pin name and function when the signal level on the pin is logic zero. – ...
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... The terms ‘cleared’, ‘inactive’, and ‘de-asserted’ are synonymous. They do not necessarily infer logic zero. In reference to the ICS1893AF, the term ‘Twisted-Pair Receiver’ refers to the set of Twisted-Pair Receive output pins (TP_RXP and TP_RXN). In reference to the ICS1893AF, the term ‘Twisted-Pair Transmitter’ refers to the set of Twisted-Pair Transmit output pins (TP_TXP and TP_TXN). Copyright © ...
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... Network Interface Cards, PC Motherboards, Printers, ACR Riser cards, Set top Boxes, and Game machines. Virtually any single Phy application utilizing the standard IEEE MII interface can use the ICS1893AF. The ICS1893AF offers the same high performance at a lower cost. Table 3-1. ICS1893AF / ICS1893Y-10 Feature Set Comparison Table ...
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... The ICS1893AF preserves the dual-purpose LED/Phy Address control pins as in the ICS1893Y-10. The captured address seeds the scrambler for lower EMI in for multiple Phy applications. • All Auto-Negotiation features are preserved in the ICS1893AF. The reset default mode is A_N enabled. The A_N parallel detect feature is preserved for legacy interoperability. • ...
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... Physical Medium Dependent sublayer (PMD) • Auto-Negotiation sublayer The ICS1893AF is transparent to the next layer of the OSI model, the link layer. The link layer has two sublayers: the Logical Link Control sublayer and the MAC sublayer. The ICS1893AF can interface directly to the MAC. ...
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... Start-of-Stream Delimiters (SSDs) and End-of-Stream Delimiters (ESDs) into the data stream. The ICS1893AF encapsulates each MAC/repeater frame, including the preamble, with an SSD and an ESD. As per the ISO/IEC Standard, the ICS1893AF replaces the first octet of each MAC preamble with an SSD and appends an ESD to the end of each MAC/repeater frame. ...
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... The ICS1893AF register bits are accessible through a standard MII (Media Independent Interface) Serial Management Port. The ICS1893AF is configured to support the MAC Interface as a 10M MII or a 100M MII. The protocol on the Medium Dependent Interface (MDI) can be configured to support either 10M or 100M operations in either half-duplex or full-duplex modes ...
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... Releases all MAC/Repeater Interface pins, which takes a maximum of 640 ns after the reset condition is removed 5.1.1.3 Hot Insertion As with the ICS189X products, the ICS1893AF reset design supports ‘hot insertion’ of its MII. (That is, the ICS1893AF can connect its MAC/Repeater Interface to a MAC/repeater while power is already applied to the MAC/repeater.) ICS1893AF, Rev. D 10/26/04 Operations” ...
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... Section 5.1.1.1, “Entering Exiting Hardware Reset After the signal on the RESETn pin transitions from a low to a high state, the ICS1893AF completes in 640 ns (that is REF_IN clocks) steps 1 through 5, listed in five steps are completed, the Serial Management Port is ready for normal operations, but this action does not signify the end of the reset cycle ...
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... LL, LH, and LMX Management Register bits are re-initialized to their default values. • During a reset, the ICS1893AF sets all of its Management Register bits to their default values. It does not maintain the state of any Management Register bit. For more information on power-down operations, see the following: • ...
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... For example, if the ICS1893AF supports 100Base-TX and 10Base-T modes – but its link partner supports 100Base-TX and 100Base-T4 modes – the two devices automatically select 100Base-TX as the highest-performance common operating mode ...
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... ISO/IEC 8802-3 standard. In the 100Base-TX mode, the ICS1893AF is a 100M translator between a MAC and the physical transmission medium. As such, the ICS1893AF has two interfaces, both of which are fully configurable: one to the MAC/repeater and one to the Link Segment. In 100Base-TX mode, the ICS1893AF provides the following functions: • ...
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... ICS1893AF Data Sheet - Release Chapter 6 Interface Overviews The ICS1893AF MAC/Repeater Interface is fully configurable, thereby allowing it to accommodate many different applications. This chapter includes overviews of the following MAC/repeater-to-PHY interfaces: • Section 6.1, “MII Data Interface” • Section 6.2, “Serial Management Interface” ...
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... PHY and the MAC as framed, 4-bit parallel nibbles. In addition, the interface also provides status and control signals to synchronize the transfers. The ICS1893AF provides a full complement of the ISO/IEC-specified MII signals. Its MII has both a transmit and a receive data path to synchronously exchange 4 bits of data (that is, nibbles). ...
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... ICS1893AF. The ISO/IEC standard also specifies a frame structure and protocol for this interface as well as a set of Management Registers that provide the STA with access to a PHY such as the ICS1893AF. A Serial Management Interface is comprised of two signals: a bi-directional data pin (MDIO) along with an associated input pin for a clock (MDC) ...
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... The ICS1893AF supplies the power to the transformer. (No VDD connection is required.) • The ICS1893AF TP_CT pin is connected directly to the transformer transmit center tap connection and is bypassed to ground with a 100-pF capacitor. The transformer center tap must not connect to the resistor/inductor network. Note: 1 ...
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... No bypass capacitor is used with the receive transformer center tap. • A 4.7-pF capacitor must be included across the ICS1893AF side of the receive transformer. Note: 1. Keep leads as short as possible. 2. Install the resistor network as close to the ICS1893AF as possible. Figure 6-2. ICS1893AF Receiver Twisted Pair TP_RXP 18 4 ...
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... MHz ±50 parts per million. This accuracy is necessary to meet the interface requirements of the ISO/IEEE 8802-3 standard, specifically clauses 22.2.2.1 and 24.2.3.4. The ICS1893AF supports two clock source configurations: a CMOS oscillator or a CMOS driver. The input to REF_IN is CMOS (10% to 90% VDD), not TTL. Alternately, a 25MHz crystal may be used. The Oscillator specifications are shown in Table 6 ...
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... If a crystal is used as the clocking source, connect it to both the Ref_in (pin 47) and Ref_out (pin 46) pins of the ICS1893AF. A pair of bypass capacitors on either side of the crystal are connected to ground. The crystal is used in the parallel resonance or anti-resonance mode. The value of the bypass caps serve to adjust the final frequency of the crystal oscillation ...
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... A software reset does not affect the state of a multi-function configuration pin. During a software reset, all multi-function configuration pins are outputs. 3. Each multi-function configuration pin must be pulled either up or down with a resistor to establish the address of the ICS1893AF. LEDs may be placed in series with these resistors to provide a designated status indicator as described in Table 6-3. Caution: All pins listed in Table 6-3 must not float ...
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... ICS1893AF Data Sheet - Release Figure 6-4 shows typical biasing and LED connections for the ICS1893AF. Figure 6-4. ICS1893AF LED - PHY Interface P4RD P3TD 8 6 REC TRANS 10K 10K This circuit decodes to PHY address = 1. Notes: 1. All LED pins must be set during reset. ...
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... ICS1893AF Data Sheet - Release Chapter 7 Functional Blocks This chapter discusses the following ICS1893AF functional blocks. • Section 7.1, “Functional Block: Media Independent Interface” • Section 7.2, “Functional Block: Auto-Negotiation” • Section 7.3, “Functional Block: 100Base-X PCS and PMA Sublayers” ...
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... The Media Independent Interface (MII) consists of two primary components interface between a MAC (Media Access Control sublayer) and the PHY (that is, the ICS1893AF). This MAC-PHY part of the MII consists of three subcomponents synchronous Transmit interface that includes the following signals: ...
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... ICS1893AF monitors the link and automatically selects the 10Base-T operating mode – even though the remote link partner does not support auto-negotiation. This process, called parallel detection, is automatic and transparent to the remote link partner and allows the ICS1893AF to function seamlessly with existing legacy network structures without any management intervention. ...
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... The ICS1893AF obtains the data for its FLP bursts from the Auto-Negotiation Advertisement Register (Register 4). 3. Both the ICS1893AF and the remote link partner substitute Fast Link Pulse (FLP) bursts in place of the Normal Link Pulses (NLPs). In each FLP burst, the ICS1893AF transmits information on its technology capability through its Link Control Word, which includes link configuration and status data ...
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... Auto-Negotiation Expansion Register’s Parallel Detection Fault bit (bit 6.4). 7.2.3 Auto-Negotiation: Remote Fault Signaling If the remote link partner detects a fault, the ICS1893AF reports the remotely detected fault to the STA by setting to logic one the Remote Fault Detected bit(s), 1.4, 5.13, 17.1, and 19.13. In general, the reception of a remote fault means that the remote link partner has a problem with the integrity of its receive channel ...
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... Monitor”. After the Auto-Negotiation Arbitration State Machine reaches its final state (which is Auto-Negotiation Complete), only an STA read of the QuickPoll Detailed Status Register or an ICS1893AF reset can alter these status bits. Any of the following situations initiates a restart of the ICS1893AF Auto-Negotiation sublayer: • ...
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... STA can determine the cause of the link failure by using the outputs of the ICS1893AF Auto-Negotiation Progress Monitor. The Auto-Negotiation Progress Monitor provides the STA with four status bits of data to indicate both the history and the present state of the auto-negotiation process ...
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... ICS1893AF Data Sheet - Release 7.3 Functional Block: 100Base-X PCS and PMA Sublayers The ICS1893AF is fully compliant with clause 24 of the ISO/IEC specification, which defines the 100Base-X Physical Coding sublayer (PCS) and Physical Medium Attachment (PMA) sublayers. 7.3.1 PCS Sublayer The ICS1893AF 100Base-X PCS sublayer provides two interfaces: one to a MAC/repeater and the other to the ICS1893AF PMA sublayer. An ICS1893’ ...
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... Full-duplex mode, COL is always FALSE. 7.3.3.2 PMA Transmit Module The ICS1893AF PMA Transmit module accepts a serial bit stream from its PCS and converts the data into NRZI format. Subsequently, the PMA passes the NRZI bit stream to the Twisted-Pair Physical Medium Dependent (TP-PMD) sublayer. ...
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... Both the PCS and PMA sublayers have Receive modules. 7.3.4.1 PCS Receive Module The ICS1893AF PCS Receive module accepts both a serial bit stream and a clock signal from the PMA sublayer. The PCS Receive module converts the bit stream from a serial format to a parallel format and then processes the data to detect the presence of a carrier ...
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... A Halt symbol, it sets the Halt Symbol Detected bit in its QuickPoll Detailed Status Register (bit 17.6) to logic one. Note: An STA can force the ICS1893AF to transmit symbols that are typically classified as invalid, by both (1) setting the Extended Control Register’s Transmit Invalid Codes bit (bit 16.2) to logic one and (2) asserting the associated TXER signal. For more information, see Error Code Test (bit ICS1893AF, Rev ...
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... Baseline wander adversely affects the noise immunity of the receiver, because the ‘baseline’ signal moves or ‘wanders’ from its nominal DC value. The ICS1893AF uses a unique technique to restore the DC component ‘lost’ by the medium result, the design is very robust, immune to noise and independent of the data stream ...
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... The DSP-based adaptive equalizer uses a technique that compensates for a wide range of cable lengths. The optimizing parameter for the equalization process is the overall bit error rate of the ICS1893AF. This technique closes the loop on the entire data reception process and provides a very high overall reliability. ...
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... ICS1893AF Data Sheet - Release 7.4.7 100Base-TX Operation: Auto Polarity Correction The ICS1893AF can sense and then automatically correct a signal polarity that is reversed on its Twisted-Pair Receiver inputs. A signal polarity reversal occurs when the input signals on the TP_RXP and TP_RXN pins are crossed or swapped (a problem that can occur during network installation or wiring). This function is primarily a 10Base-T function, however also active during Auto-Negotiation ...
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... Operation: Manchester Encoder/Decoder During data transmission the ICS1893AF acquires data from its MAC/Repeater Interface in either 4-bit nibbles serial bit stream. The ICS1893AF converts this data into a Manchester-encoded signal for presentation to its MDI, as required by the ISO/IEC specification Manchester-encoded signal, all logic: • ...
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... Link Status bit or the last reset of the ICS1893AF. • One, a valid link is established. The ICS1893AF Link Status bit is a latching low (LL) bit. (For more information on latching high and latching low bits, see Section 8.1.4.1, “Latching High Bits” The criteria used by the Link Monitor Function to declare a link either valid (that is, ‘established’ or ‘up’) or invalid (that is, ‘ ...
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... When a link is invalid and the Link Monitor Function detects the presence of data, the ICS1893AF does not transition the link to the valid state until after the reception of the present packet is complete. ...
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... The ICS1893AF is in full-duplex mode. – The ICS1893AF detects a link failure. – The ICS1893AF SQE Test Inhibit bit (bit 18.2) in the 10Base-T Operations Register is logic one. [This bit provides the Station Management entity (STA) with the ability to disable the SQE Test function.] Note: 1 ...
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... Normal Link Pulses (NLPs). In 10Base-T mode, an ICS1893AF transmits and receives NLPs when its link is in the Idle state. In 100Base-TX mode, an ICS1893AF transmits and receives NLPs during Auto-Negotiation. An STA can control this feature using the 10Base-T Operations Register bit 18.3, the Auto Polarity-Inhibit bit. When this bit is logic: • ...
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... Management Frame Structure The Serial Management Interface is a synchronous, bi-directional, two-wire, serial interface for the exchange of configuration, control, and status data between a PHY, such as an ICS1893AF, and an STA. All data transferred on an MDIO signal is synchronized by its MDC signal. The PHY and STA exchange data through a pre-defined register set ...
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... A valid Management Frame includes an operation code (OP) immediately following the start-of-frame delimiter. There are two valid operation codes: one for reading from a management register, 10b, and one for writing to a management register, 01b. The ICS1893AF does not respond to the codes 00b and 11b, which the ISO/IEC specification defines as invalid. ...
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... MDIO pin to logic zero for the second bit time. • Write, an ICS1893AF waits while the STA transmits a logic one, followed by a logic zero on its MDIO pin. 7.6.2.8 Management Frame Data A valid management frame includes a 16-bit Data field for exchanging the register contents between the ICS1893AF and the STA ...
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... ICS1893AF Data Sheet - Release Chapter 8 Management Register Set The tables in this chapter detail the functionality of the bits in the management register set. The tables include the register locations, the bit positions, the bit definitions, the STA Read/Write Access Types, the default bit values, and any special bit functions or capabilities (such as self-clearing). Following each table is a description of each bit. This chapter includes the following sections: • ...
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... Reserved by IEEE 16 through 31 Vendor-Specific (ICS) Registers Table 8-2 lists the ICS-specific registers that the ICS1893AF implements. These registers enhance the performance of the ICS1893AF and provide the Station Management entity (STA) with additional control and status capabilities. Table 8-2. ICS-Specific Registers Register Address 16 ...
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... Read/Write Zero R/W0 8.1.3 Management Register Bit Default Values The tables in this chapter specify for each register bit the default value, if one exists. The ICS1893AF sets all Management Register bits to their default values after a reset. ICS1893AF Management Register bits. Table 8-4. Range of Possible Valid Default Values for ICS1893AF Register Bits Default Condition – ...
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... STA access. The SC bits have a default value of logic zero and are triggers to begin execution of a function. When the STA writes a logic one bit, the ICS1893AF begins executing the function assigned to that bit. After the ICS1893AF completes executing the function, it clears the bit to indicate that the action is complete ...
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... Reserved bits. 8.2.1 Reset (bit 0.15) This bit controls the software reset function. Setting this bit to logic one initiates an ICS1893AF software reset during which all Management Registers are set to their default values and all internal state machines are set to their idle state. For a detailed description of the software reset process, see “ ...
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... HW/SW input pin and the Auto-Negotiation Enable bit (bit 0.12). When the ICS1893AF is configured for: • Hardware mode (that is, the HW/SW pin is logic zero), the ICS1893AF isolates this bit 0.13 and uses the 10/100SEL input pin to establish the data rate for the ICS1893AF. In this Hardware mode: – Bit 0.13 is undefined. ...
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... Management Interface). The default value for bit 0.10 depends upon the PHY address of • Is equal to 00000b, then the default value of bit 0.10 is logic one, and the ICS1893AF isolates itself from the MAC/Repeater Interface. • Is not equal to 00000b, then the default value of bit 0.10 is logic zero, and the ICS1893AF does not isolate its MAC/Repeater Interface ...
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... HW/SW input pin and the Auto-Negotiation Enable bit (bit 0.12). When the ICS1893AF is configured for: • Hardware mode (that is, the HW/SW pin is logic zero), the ICS1893AF isolates bit 0.8 and uses the DPXSEL input pin to establish the Duplex mode for the ICS1893AF. In this Hardware mode: – Bit 0.8 is undefined. ...
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... As per the IEEE Std 802.3u, during any write operation to any bit in this register, the STA must write the default value to all Reserved bits. 8.3.1 100Base-T4 (bit 1.15) The STA reads this bit to learn if the ICS1893AF can support 100Base-T4 operations. Bit 1.15 of the ICS1893AF is permanently set to logic zero, which informs an STA that the ICS1893AF cannot support 100Base-T4 operations. ...
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... Therefore, when an STA reads the Status Register, the STA is informed that the ICS1893AF supports 10Base-T, half-duplex operations.) Bit 1.11 of the ICS1893AF Status Register is a Command Override Write bit., which allows an STA to alter the default value of this bit. [See the description of bit 16.15, the Command Override Write Enable bit, in Section 8.11, “ ...
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... This default value ensures that bit 1.6 is backward compatible with the ICS1890, which does not have this capability. As the means of enabling this feature, the ICS1893AF implements bit 1 Command Override Write bit, instead Read-Only bit as in the ICS1890. An STA uses the bit 1.6 to enable MF Preamble Suppression in the ICS1893AF ...
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... ICS1893AF Data Sheet - Release 8.3.9 Remote Fault (bit 1.4) An STA reads bit 1.4 to determine if a Remote Fault exists. The ICS1893AF sets bit 1.4 based on the Remote Fault bit received from its remote link partner. The ICS1893AF receives the Remote Fault bit as part of the Link Code Word exchanged during the auto-negotiation process ...
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... Operation: Link 8.3.12 Jabber Detect (bit 1.1) The purpose of this bit is to allow an STA to determine if the ICS1893AF detects a Jabber condition as defined in the ISO/IEC specification.The ICS1893AF Jabber Detection function is controlled by the Jabber Inhibit bit in the 10Base-T Operations register (bit 18.5). To detect a Jabber condition, first the ICS1893AF Jabber Detection function must be enabled. When bit 18.5 is logic: • ...
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... ICS1893AF Data Sheet - Release 8.4 Register 2: PHY Identifier Register Table 8-7 lists the bits for PHY Identifier Register (Register 2), which is one of two PHY Identifier Registers that are part of a set defined by the ISO/IEC specification set, the PHY Identifier Registers (Registers 2 and 3) include a unique, 32-bit PHY Identifier composed from the following: • ...
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... ICS1893AF Data Sheet - Release IEEE-Assigned Organizationally Unique Identifier (OUI) For each manufacturing organization, the IEEE assigns an 3-octet OUI. For Integrated Circuit Systems, Inc. the IEEE-assigned 3-octet OUI is 00A0BEh. The binary representation of an OUI is formed by expressing each octet as a sequence of eight bits, from least significant to most significant, and from left to right ...
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... ICS1893AF Data Sheet - Release 8.5 Register 3: PHY Identifier Register Table 8-9 lists the bits for PHY Identifier Register (Register 3), which is one of two PHY Identifier Registers that are part of a set defined by the ISO/IEC specification. This register stores the following: • Part of the OUI [see the text in • ...
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... ICS1893AF Data Sheet - Release 8.5.2 Manufacturer’s Model Number (bits 3.9:4) The model number for the ICS1893AF is 4 (decimal stored in bit 3.9:4 as 00100b. 8.5.3 Revision Number (bits 3.3:0) Table 8-10 lists the valid ICS1893AF revision numbers, which are 4-bit binary numbers stored in bits 3.3:0. ...
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... Zero, then the ICS1893AF indicates to its remote link partner that these features are disabled. (Although the default value of this bit is logic zero, the ICS1893AF does support the Next Page function.) • One, then the ICS1893AF advertises to its remote link partner that this feature is enabled. ...
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... Code Word that the ICS1893AF exchanges with its remote link partner. The ICS1893AF sets this bit to logic one whenever it detects a problem with the link, locally. The data in this register is sent to the remote link partner to inform it of the potential problem. If the ICS1893AF does not detect a link fault, it clears bit 4.13 to logic zero. ...
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... ICS1893AF to provide these technologies. Note: 1. The ICS1893AF does not alter the value of the Status Register bits based on the TAF bits in register 4, as the ISO/IEC definitions for the Status Register bits require these bits to indicate all the capabilities of the ICS1893AF ...
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... These bits indicate to the remote link partner the type of message being sent during the auto-negotiation process. The ICS1893AF supports IEEE Std. 802.3, represented by a value of 00001b in bits 4.4:0. The ISO/IEC 8802-3 standard defines the Selector Field technologies in Annex 28A. ...
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... During the auto-negotiation process, the ICS1893AF advertises (that is, exchanges) the capability data with its remote link partner using a pre-defined Link Code Word. The value of the Link Control Word received from its remote link partner establishes the value of the bits in this register ...
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... Zero, it indicates that the remote link partner has not received the ICS1893AF Link Control Word. • One, it indicates to the ICS1893AF / STA that the remote link partner has acknowledged reception of the ICS1893AF Link Control Word. 8.7.3 Remote Fault (bit 5.13) The ISO/IEC specification defines bit 5.13 as the Remote Fault bit. This bit is set based on the Link Control Word received from the remote link partner. When this bit is a logic: • ...
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... Writes to a reserved bit, the STA must use the default value specified in this data sheet. ICS uses some reserved bits to invoke auxiliary functions. To ensure proper operation of the ICS1893AF, an STA must maintain the default value of these bits. Therefore, ICS recommends that an STA always write the default value of any reserved bits during all management register write operations ...
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... Next Page bit in its Link Control Word. 8.8.4 Next Page Able (bit 6.2) Bit 6 status bit that reports the capabilities of the ICS1893AF to support the Next Page features of the auto-negotiation process. The ICS1893AF sets this bit to a logic one to indicate that it can support these features ...
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... ICS1893AF Data Sheet - Release 8.9 Register 7: Auto-Negotiation Next Page Transmit Register Table 8-14 lists the bits for the Auto-Negotiation Next Page Transmit Register, which establishes the contents of the Next Page Link Control Word that is transmitted during Next Page Operations. This table is compliant with the ISO/IEC specification ...
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... Zero, it indicates that the ICS1893AF cannot comply with the message. • One, it indicates to the remote link partner that the ICS1893AF can comply with the message. 8.9.5 Toggle (bit 7.11) The Toggle (T) bit (bit 7.11) is used to synchronize the transmission of Next Page messages with the remote link partner ...
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... ICS1893AF Data Sheet - Release 8.10 Register 8: Auto-Negotiation Next Page Link Partner Ability Register Table 8-15 lists the bits for the Auto-Negotiation Next Page Link Partner Ability Register, which establishes the contents of the Next Page Link Control Word that is transmitted during Next Page Operations. This table is compliant with the ISO/IEC specification ...
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... Zero, it indicates that the ICS1893AF cannot comply with the message. • One, it indicates to the remote link partner that the ICS1893AF can comply with the message. If the previous Next Page Link Control Word Toggle bit has a value of logic: • Zero, then the Toggle bit is set to logic one. ...
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... ICS1893AF Data Sheet - Release 8.11 Register 16: Extended Control Register Table 8-16 lists the bits for the Extended Control Register, which the ICS1893AF provides to allow an STA to customize the operations of the device. Note: 1. For an explanation of acronyms used in 2. During any write operation to any bit in this register, the STA must write the default value to all Reserved bits ...
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... Pins”). The PHY address is then latched into this register. (The value of each of the PHY Address bits is unaffected by a software reset.) 8.11.4 Stream Cipher Scrambler Test Mode (bit 16.5) The Stream Cipher Scrambler Test Mode bit is used to force the ICS1893AF to lose LOCK, thereby requiring the Stream Cipher Scrambler to resynchronize. 8.11.5 ICS Reserved (bit 16.4) See Section 8.11.2, “ ...
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... ICS1893AF Data Sheet - Release 8.11.7 Invalid Error Code Test (bit 16.2) The Invalid Error Code Test bit allows an STA to force the ICS1893AF to transmit symbols that are typically classified as invalid. The purpose of this test bit is to permit thorough testing of the 4B/5B encoding and the serial transmit data stream by allowing generation of bit patterns that are considered invalid by the ISO/IEC 4B/5B definition ...
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... Note: 1. For an explanation of acronyms used in 2. Most of this register’s bits are latching high or latching low, which allows the ICS1893AF to capture and save the occurrence of an event for an STA to read. (For more information on latching high and latching low bits, see Section 8.1.4.1, “ ...
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... ICS1893AF Data Sheet - Release 8.12.1 Data Rate (bit 17.15) The Data Rate bit indicates the ‘selected technology’. If the ICS1893AF is in: • Hardware mode, the value of this bit is determined by the 10/100SEL input pin. • Software mode, the value of this bit is determined by the Data Rate bit 0.13. ...
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... Auto-Negotiation Completed Successfully 8.12.4 100Base-TX Receive Signal Lost (bit 17.10) The 100Base-TX Receive Signal Lost bit indicates to an STA whether the ICS1893AF has lost its 100Base-TX Receive Signal. If this bit is set to a logic: • Zero, it indicates the Receive Signal has remained valid since either the last read or reset of this register. ...
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... When the ICS1893AF is receiving a packet, it examines each received Symbol to ensure the data is error free error occurs, the port indicates this condition to the MAC/repeater by asserting the RXER signal. In addition, the ICS1893AF sets its Invalid Symbol bit to logic one. Therefore, if this bit is set to a logic: • ...
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... The Premature End bit indicates to an STA the detection of two consecutive Idles in a 100Base data stream by the ICS1893AF. During reception of a valid packet, the ICS1893AF examines each symbol to ensure that the data being passed to the MAC/Repeater Interface is error free. If two consecutive Idles are encountered, it indicates this condition to the MAC/repeater by setting this bit ...
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... ICS1893AF Data Sheet - Release 8.12.12 Jabber Detect (bit 17.2) Bit 17.2 is functionally identical to bit 1.1. The Jabber Detect bit indicates whether a jabber condition has occurred. This bit is a 10Base-T function. 8.12.13 Remote Fault (bit 17.1) Bit 17.1 is functionally identical to bit 1.4. ...
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... Squelch inhibit 8.13.1 Remote Jabber Detect (bit 18.15) The Remote Jabber Detect bit is provided to indicate that an ICS1893AF port has detected a Jabber Condition on its receive path. This bit is reset to logic zero on a read of the 10Base-T operations register. When this bit is logic: • ...
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... ICS1893AF Data Sheet - Release 8.13.2 Polarity Reversed (bit 18.14) The Polarity Reversed bit is used to inform an STA whether the ICS1893AF has detected that the signals on the Twisted-Pair Receive Pins (TP_RXP and TP_RXN) are reversed. When the signal polarity is: • Correct, the ICS1893AF sets bit 18. logic zero. ...
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... ICS1893AF Data Sheet - Release 8.13.8 Link Loss Inhibit (bit 18.1) The Link Loss Inhibit bit allows an STA to prevent the ICS1893AF from dropping the link in 10Base-T mode. When an STA sets this bit to logic: • Zero, the state machine behaves normally and the link status is based on the signaling detected Twisted- Pair Receiver inputs. • ...
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... ICS1893AF Data Sheet - Release 8.14 Register 19: Extended Control Register 2 The Extended Control Register provides more refined control of the internal ICS1893AF operations. Note: 1. For an explanation of acronyms used in 2. During any write operation to any bit in this register, the STA must write the default value to all Reserved bits ...
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... See Section 8.11.2, “ICS Reserved (bits 8.14.5 Twisted Pair Tri-State Enable, TPTRI (bit 19.7) The ICS1893AF provides a Twisted Pair Tri-State Enable bit. This bit forces the TP_TXP and TP_TXN signals to a high-impedance state. When this bit is set to logic: • Zero, the Twisted Pair Interface is operational. ...
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... ICS1893AF Data Sheet - Release Chapter 9 Pin Diagram, Listings, and Descriptions 9.1 ICS1893AF Pin Diagram POAC 1 VSS 2 P1CL 3 P2LI 4 VSS 5 P3TD 6 VDD 7 P4RD 8 10/100 9 TP_CT 10 VSS 11 TP_TXP 12 TP_TXN 13 VDD 14 10TCSR 15 100TCSR 16 VSS 17 TP_RXP 18 TP_RXN 19 VDD 20 VSS 21 RESET_N 22 VSS 23 VDD 24 ICS1893AF, Rev D 10/26/04 ...
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... ICS1893AF Data Sheet - Release 9.2 ICS1893AF Pin Descriptions Table 9-1. MAC Interface Pins Signal Name MDIO MDC RXD3 RXD2 RXD1 RXD0 RXDV RXCLK RXER TXCLK TXEN TXD0 TXD1 TXD2 TXD3 COL CRS Table 9-2. Transformer Interface Pins Signal Name TP_TXP TP_TXN ...
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... REFIN RFOUT RESETn 9.2.1 Transformer Interface Pins The tables in this section list the ICS1893AF pins by their functional grouping. Table 9-5 lists the pins for the transformer interface group of pins. Table 9-5. Transformer Interface Pins Pin Pin Pin Name ...
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... Note: 1. During either a power-on reset or a hardware reset, each multi-function configuration pin is an input that is sampled when the ICS1893AF exits the reset state. After sampling is complete, these pins are output pins that can drive status LEDs software reset does not affect the state of a multi-function configuration pin. During a software reset, all multi-function configuration pins are outputs ...
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... High, that address is set to logic one output pin: • When the signal on this pin is: – De-asserted, this state indicates the ICS1893AF does not detect any collisions. – Asserted, this state indicates the ICS1893AF detects collisions. • The ICS1893AF asserts its Collision LED for a period of approximately 70 msec when it detects a collision ...
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... This multi-function configuration pin is: – An input pin during either a power-on reset or a hardware reset. In this case, this pin configures the ICS1893AF when either hardware mode or software mode. – An output pin following reset. In this case, this pin provides activity status of the ICS1893. ...
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... Reference Output. This pin is used with a crystal. (System) Reset (Active Low). • When the signal on this active-low pin is logic: – Low, the ICS1893AF is in hardware reset. – High, the ICS1893AF is operational. • For more information on hardware resets, see the following: – ...
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... Note: The signal on the CRS pin is not synchronous to the signal on either the RXCLK or TXCLK pin. Management Data Clock. The ICS1893AF uses the signal on the MDC pin to synchronize the transfer of management information between the ICS1893AF and the Station Management Entity (STA), using the serial MDIO data line. The MDC signal is sourced by the STA. Copyright © ...
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... The ICS1893AF, to transfer status information. All transfers and sampling are synchronous with the signal on the MDC pin. Note: If the ICS1893AF used in an application that uses the mechanical MII specification, MDIO must have a 1.5 k ±5% pull-up resistor at the ICS1893AF end and ±5% pull-down resistor at the station management end ...
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... Errors are detected during the reception of valid frames – A False Carrier is detected Note ICS1893AF asserts a signal on the RXER pin upon detection of a False Carrier so that repeater applications can prevent the propagation of a False Carrier. 2. The RXER signal always transitions synchronously with RXCLK. ...
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... TXD0 is the least-significant bit and TXD3 is the most-significant bit of the MII transmit data nibble received from the MAC/repeater. • The ICS1893AF samples its TXEN signal to determine when data is available for transmission. When TXEN is asserted, the signals on a the TXD[3:0] pins are sampled synchronously on the rising edges of the TXCLK signal ...
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... ICS1893AF Data Sheet - Release 9.2.5 Ground and Power Pins Table 9-9. Ground and Power Pins Signal Name VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS ICS1893AF, Rev. D 10/26/04 Chapter 9 Pin Diagram, Listings, and Descriptions Pin No ...
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... Stresses above these ratings can permanently damage the ICS1893AF. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the ICS1893AF at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability ...
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... ICS1893AF Data Sheet - Release 10.3 Recommended Component Values Table 10-3. Recommended Component Values for ICS1893AF Parameter Oscillator Frequency 10TCSR Resistor Value 100TCSR Resistor Value LED Resistor Value † There are two IEEE Std. 802.3 requirements that drive the tolerance for the frequency of the oscillator. ...
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... Power-Down Supply Current† Reset † These supply current parameters are measured through VDD pins to the ICS1893AF. The supply current parameters include external transformer currents. ‡ Measurements taken with 100% data transmission and the minimum inter-packet gap. 10.4.2 DC Operating Characteristics for TTL Inputs and Outputs Table 10-5 lists the 3 ...
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... Input High Voltage Input Low Voltage 10.4.4 DC Operating Characteristics for Media Independent Interface Table 10-7 lists DC operating characteristics for the Media Independent Interface (MII) for the ICS1893AF. Table 10-7. DC Operating Characteristics for Media Independent Interface Parameter MII Input Pin Capacitance MII Output Pin Capacitance MII Output Drive Impedance ICS1893AF, Rev ...
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... ICS1893AF Data Sheet - Release 10.5 Timing Diagrams 10.5.1 Timing for Clock Reference In (REF_IN) Pin Table 10-8 lists the significant time periods for signals on the clock reference in (REF_IN) pin. shows the timing diagram for the time periods. Note: The REF_IN switching point is 50% of VDD. ...
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... ICS1893AF Data Sheet - Release 10.5.2 Timing for Transmit Clock (TXCLK) Pins Table 10-9 lists the significant time periods for signals on the Transmit Clock (TXCLK) pins for the various interfaces. Figure 10-3 shows the timing diagram for the time periods. Table 10-9. Transmit Clock Timing ...
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... ICS1893AF Data Sheet - Release 10.5.3 Timing for Receive Clock (RXCLK) Pins Table 10-10 lists the significant time periods for signals on the Receive Clock (RXCLK) pins for the various interfaces. Figure 10-4 shows the timing diagram for the time periods. Table 10-10. MII Receive Clock Timing ...
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... ICS1893AF Data Sheet - Release 10.5.4 100M MII: Synchronous Transmit Timing Table 10-11 lists the significant time periods for the 100M MII Interface synchronous transmit timing. The time periods consist of timings of signals on the following pins: • TXCLK • TXD[3:0] • TXEN • ...
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... ICS1893AF Data Sheet - Release 10.5.5 10M MII: Synchronous Transmit Timing Table 10-12 lists the significant time periods for the 10M MII synchronous transmit timing. The time periods consist of timings of signals on the following pins: • TXCLK • TXD[3:0] • TXEN • TXER Figure 10-6 shows the timing diagram for the time periods ...
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... ICS1893AF Data Sheet - Release 10.5.6 100M/MII Media Independent Interface: Synchronous Receive Timing Table 10-13 lists the significant time periods for the MII / 100M Stream Interface synchronous receive timing. The time periods consist of timings of signals on the following pins: • RXCLK • RXD[3:0] • ...
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... MDC Rise Time to MDIO Valid t5 MDIO Setup Time to MDC t6 MDIO Hold Time after MDC † The ICS1893AF is tested at 25 MHz (a 40-ns period) with a 50-pF load. Designs must account for all board loading of MDC. Figure 10-8. MII Management Interface Timing Diagram MDC t1 ...
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... ICS1893AF Data Sheet - Release 10.5.8 10M Media Independent Interface: Receive Latency Table 10-15 lists the significant time periods for the 10M MII timing. The time periods consist of timings of signals on the following pins: • TP_RX (that is, the MII TP_RXP and TP_RXN pins) • ...
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... ICS1893AF Data Sheet - Release 10.5.9 10M Media Independent Interface: Transmit Latency Table 10-16 lists the significant time periods for the 10M MII transmit latency. The time periods consist of timings of signals on the following pins: • TXEN • TXCLK • TXD (that is, TXD[3:0]) • ...
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... ICS1893AF Data Sheet - Release 10.5.10 100M / MII Media Independent Interface: Transmit Latency Table 10-17 lists the significant time periods for the MII / 100 Stream Interface transmit latency. The time periods consist of timings of signals on the following pins: • TXEN • TXCLK • ...
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... ICS1893AF Data Sheet - Release 10.5.11 100M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) Table 10-18 lists the significant time periods for the 100M MII carrier assertion/de-assertion during half-duplex transmission. The time periods consist of timings of signals on the following pins: • TXEN • TXCLK • ...
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... ICS1893AF Data Sheet - Release 10.5.12 10M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) Table 10-19 lists the significant time periods for the 10M MII carrier assertion/de-assertion during half-duplex transmission. The time periods consist of timings of signals on the following pins: • TXEN • TXCLK • ...
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... ICS1893AF Data Sheet - Release 10.5.13 100M MII Media Independent Interface: Receive Latency Table 10-20 lists the significant time periods for the 100M MII / 100M Stream Interface receive latency. The time periods consist of timings of signals on the following pins: • TP_RX (that is, TP_RXP and TP_RXN) • ...
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... ICS1893AF Data Sheet - Release 10.5.14 100M Media Independent Interface: Input-to-Carrier Assertion/De-Assertion Table 10-21 lists the significant time periods for the 100M MDI input-to-carrier assertion/de-assertion. The time periods consist of timings of signals on the following pins: • TP_RX (that is, TP_RXP and TP_RXN) • CRS • ...
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... ICS1893AF Data Sheet - Release 10.5.15 Reset: Power-On Reset Table 10-22 lists the significant time periods for the power-on reset. The time periods consist of timings of signals on the following pins: • VDD • TXCLK Figure 10-16 shows the timing diagram for the time periods. ...
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... ICS1893AF Data Sheet - Release 10.5.16 Reset: Hardware Reset and Power-Down Table 10-23 lists the significant time periods for the hardware reset and power-down reset. The time periods consist of timings of signals on the following pins: • REF_IN • RESETn • TXCLK Figure 10-17 shows the timing diagram for the time periods ...
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... ICS1893AF Data Sheet - Release 10.5.17 10Base-T: Heartbeat Timing (SQE) Table 10-24 lists the significant time periods for the 10Base-T heartbeat (that is, the Signal Quality Error). The time periods consist of timings of signals on the following pins: • TXEN • TXCLK • COL Figure 10-18 shows the timing diagram for the time periods ...
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... ICS1893AF Data Sheet - Release 10.5.18 10Base-T: Jabber Timing Table 10-25 lists the significant time periods for the 10Base-T jabber. The time periods consist of timings of signals on the following pins: • TXEN • TP_TX (that is, TP_TXP and TP_TXN) • COL Figure 10-19 shows the timing diagram for the time periods. ...
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... ICS1893AF Data Sheet - Release 10.5.19 10Base-T: Normal Link Pulse Timing Table 10-26 lists the significant time periods for the 10Base-T Normal Link Pulse (which consists of timings of signals on the TP_TXP pins). Table 10-26. 10Base-T Normal Link Pulse Timing Time Period t1 Normal Link Pulse Width ...
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... ICS1893AF Data Sheet - Release 10.5.20 Auto-Negotiation Fast Link Pulse Timing Table 10-27 lists the significant time periods for the ICS1893AF Auto-Negotiation Fast Link Pulse. The time periods consist of timings of signals on the following pins: • TP_TXP • TP_TXN Figure 10-21 shows the timing diagram for one pair of these differential signals, for example TP_TXP minus TP_TXN ...
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... ICS1893AF Data Sheet - Release Chapter 11 Physical Dimensions of ICS1893AF Package Figure 11-1. ICS1893AF Physical Dimensions INDEX INDEX AREA AREA SYMBOL α VARIATIONS Reference Doc.: JEDEC Publication 95, MO-118 10-0034 ICS1893AF, Rev D 10/26/04 Chapter 11 Physical Dimensions of ICS1893AF 45˚ 45˚ SEATING SEATING b PLANE PLANE .10 (.004) C ...
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... ICS1893AF Data Sheet - Release Chapter 12 Ordering Information Figure 12-1. shows ordering information for the ICS1893AF. "T" = Tape and Reel. Part / Order Number ICS1893AFLFT ICS1893AFILFT ICS1893AFLF ICS1893AFILF ICS1893AF, Rev. D 10/26/04 Marking Package 1893AFLF 48-Lead 300-mil SSOP 1893AFILF 48-Lead 300-mil SSOP 1893AFLF 48-Lead 300-mil SSOP ...
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... ICS1893AF Data Sheet - Release Integrated Circuit Systems, Inc. Corporate Headquarters: San Jose, CA Operations: Web Site: ICS1893AF, Rev D 10/26/04 2435 Boulevard of the Generals Norristown, PA 19403 Telephone: 610-630-5300 Fax: 610-630-5399 525 Race Street San Jose, CA 95126-3448 Telephone: 408-297-1201 Fax: 408-925-9460 Email: marcom@icst.com http://www.icst.com Copyright © ...