ICS1893AF IDT, Integrated Device Technology Inc, ICS1893AF Datasheet - Page 52

• Manufacturer Part Number: ICS1893AF
• Description: PHYCEIVER LOW PWR 3.3V 48-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893AF

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Other names: 1893AF

7.6 Functional Block: Management Interface
7.6.1 Management Register Set Summary
7.6.2 Management Frame Structure
ICS1893AF, Rev D 10/26/04
As part of the MAC/Repeater Interface, the ICS1893AF provides a two-wire serial management interface
which complies with the ISO/IEC 8802-3 standard MII Serial Management Interface. This interface is used
to exchange control, status, and configuration information between a Station Management entity (STA) and
the physical layer device (PHY). The PHY and STA exchange this data through a pre-defined set of
management registers. The ISO/IEC standard specifies the following components of this serial
management interface:
•
•
•
In compliance with the ISO/IEC specification, the ICS1893AF implementation of the serial management
interface provides a bi-directional data pin (MDIO) along with a clock (MDC) for synchronizing the
exchange of data. These pins remain active in all ICS1893AF MAC/Repeater Interface modes (that is, the
10/100 MII, 100M Symbol, and 10M Serial interface modes).
The ICS1893AF implements a Management Register set that adheres to the ISO/IEC standard. This
register set (discussed in detail in
Control and Status registers and the ISO/IEC ‘Extended’ registers as well as some ICS-specific registers.
The Serial Management Interface is a synchronous, bi-directional, two-wire, serial interface for the
exchange of configuration, control, and status data between a PHY, such as an ICS1893AF, and an STA.
All data transferred on an MDIO signal is synchronized by its MDC signal. The PHY and STA exchange
data through a pre-defined register set.
The ICS1893AF complies with the ISO/IEC defined Management Frame Structure and protocol. This
structure supports both read and write operations.
Structure.
Note:
Table 7-2. Management Frame Structure Summary
PRE
SFD
OP
PHYAD
REGAD
TA
DATA
A set of registers
The frame structure
The protocol
Acronym
ICS1893AF Data Sheet - Release
The Management Frame Structure starts from and returns to an IDLE condition. However, the IDLE
periods are not part of the Management Frame Structure.
Preamble (Bit 1.6)
Start of Frame
Operation Code
PHY Address (Bits 16.10:6)
Register Address
Turnaround
Data
Frame Field
(Section 7.6.1, “Management Register Set
(Section 7.6.2, “Management Frame
Frame Function
Copyright © 2004, Integrated Circuit Systems, Inc.
Chapter 8, “Management Register
All rights reserved.
52
11..11
01
10/01 (read/write)
AAAAA
RRRRR
Z0/10 (read/write)
DDD..DD
Table 7-2
Data
Structure”)
summarizes the Management Frame
Summary”)
Set”) includes the mandatory ‘Basic’
32 ones
2 bits
2 bits
5 bits
5 bits
2 bits
16 bits
Comment
Chapter 7 Functional Blocks
October, 2004