ICS1893AF IDT, Integrated Device Technology Inc, ICS1893AF Datasheet - Page 4

• Manufacturer Part Number: ICS1893AF
• Description: PHYCEIVER LOW PWR 3.3V 48-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893AF

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Other names: 1893AF

ICS1893AF, Rev D 10/26/04
Section
Chapter 8
8.1
8.1.1
8.1.2
8.1.3
8.1.4
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
8.2.10
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
8.3.8
8.3.9
8.3.10
8.3.11
8.3.12
8.3.13
8.4
ICS1893AF Data Sheet - Release
Management Register Set ............................................................................................... 55
Introduction to Management Register Set .............................................................56
Management Register Set Outline .........................................................................56
Management Register Bit Access ..........................................................................57
Management Register Bit Default Values ..............................................................57
Management Register Bit Special Functions .........................................................58
Register 0: Control Register ...................................................................................59
Reset (bit 0.15) ......................................................................................................59
Loopback Enable (bit 0.14) ....................................................................................60
Data Rate Select (bit 0.13) .....................................................................................60
Auto-Negotiation Enable (bit 0.12) .........................................................................60
Low Power Mode (bit 0.11) ....................................................................................61
Isolate (bit 0.10) .....................................................................................................61
Restart Auto-Negotiation (bit 0.9) ..........................................................................61
Duplex Mode (bit 0.8) .............................................................................................62
Collision Test (bit 0.7) ............................................................................................62
IEEE Reserved Bits (bits 0.6:0) .............................................................................62
Register 1: Status Register ....................................................................................63
100Base-T4 (bit 1.15) ............................................................................................63
100Base-TX Full Duplex (bit 1.14) .........................................................................64
100Base-TX Half Duplex (bit 1.13) ........................................................................64
10Base-T Full Duplex (bit 1.12) .............................................................................64
10Base-T Half Duplex (bit 1.11) .............................................................................64
IEEE Reserved Bits (bits 1.10:7) ...........................................................................65
MF Preamble Suppression (bit 1.6) .......................................................................65
Auto-Negotiation Complete (bit 1.5) .......................................................................65
Remote Fault (bit 1.4) ............................................................................................66
Auto-Negotiation Ability (bit 1.3) ............................................................................66
Link Status (bit 1.2) ................................................................................................67
Jabber Detect (bit 1.1) ...........................................................................................67
Extended Capability (bit 1.0) ..................................................................................67
Register 2: PHY Identifier Register ........................................................................68
Copyright © 2004, Integrated Circuit Systems, Inc.
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Table of Contents
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