ICS1893AF IDT, Integrated Device Technology Inc, ICS1893AF Datasheet - Page 60

• Manufacturer Part Number: ICS1893AF
• Description: PHYCEIVER LOW PWR 3.3V 48-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893AF

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Other names: 1893AF

8.2.2 Loopback Enable (bit 0.14)
8.2.3 Data Rate Select (bit 0.13)
8.2.4 Auto-Negotiation Enable (bit 0.12)
ICS1893AF, Rev D 10/26/04
This bit controls the Loopback mode for the ICS1893AF. Setting this bit to logic:
•
•
This bit provides a means of controlling the ICS1893AF data rate. Its operation depends on the state of
several other functions, including the HW/SW input pin and the Auto-Negotiation Enable bit (bit 0.12).
When the ICS1893AF is configured for:
•
•
This bit provides a means of controlling the ICS1893AF Auto-Negotiation sublayer. Its operation depends
on the HW/SW input pin.
When the ICS1893AF is configured for:
•
•
Zero disables the Loopback mode.
One enables the Loopback mode by disabling the Twisted-Pair Transmitter, the Twisted-Pair Receiver,
and the collision detection circuitry. (The STA can override the ICS1893AF from disabling the collision
detection circuitry in Loopback mode by writing logic one to bit 0.7.) When the ICS1893AF is in Loopback
mode, the data presented at the MAC/repeater transmit interface is internally looped back to the
MAC/repeater receive interface. The delay from the assertion of Transmit Data Enable (TXEN) to the
assertion of Receive Data valid (RXDV) is less than 512 bit times.
Hardware mode (that is, the HW/SW pin is logic zero), the ICS1893AF isolates this bit 0.13 and uses the
10/100SEL input pin to establish the data rate for the ICS1893AF. In this Hardware mode:
Software mode (that is, the HW/SW pin is logic one), the function of bit 0.13 depends on the
Auto-Negotiation Enable bit 0.12. When the Auto-Negotiation sublayer is:
Hardware mode, (that is, the HW/SW pin is logic zero), the ICS1893AF isolates bit 0.12 and uses the
ANSEL (Auto-Negotiation Select) input pin to determine whether to enable the Auto-Negotiation
sublayer.
Note: In Hardware mode, bit 0.12 is undefined.
Software mode, (that is, the HW/SW pin is logic one), bit 0.12 determines whether to enable the
Auto-Negotiation sublayer. When bit 0.12 is logic:
– Bit 0.13 is undefined.
– The ICS1893AF provides a Data Rate Status bit (in the QuickPoll Detailed Status Register, bit 17.15),
– Enabled, the ICS1893AF isolates bit 0.13 and relies on the results of the auto-negotiation process to
– Disabled, bit 0.13 determines the data rate. In this case, setting bit 0.13 to logic:
– Zero:
– One:
ICS1893AF Data Sheet - Release
which always shows the setting of an active link.
establish the data rate.
• Zero selects 10-Mbps ICS1893AF operations.
• One selects 100-Mbps ICS1893AF operations.
• The ICS1893AF disables the Auto-Negotiation sublayer.
• The ICS1893AF bit 0.13 (the Data Rate bit) and bit 0.8 (the Duplex Mode bit) determine the data
• The ICS1893AF enables the Auto-Negotiation sublayer.
• The ICS1893AF isolates bit 0.13 and bit 0.8.
rate and the duplex mode.
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
60
Chapter 8 Management Register Set
October, 2004