PIC18F2320-I/SP Microchip Technology Inc., PIC18F2320-I/SP Datasheet - Page 41

• Manufacturer Part Number: PIC18F2320-I/SP
• Description: Microcontroller; 8 KB Flash; 512 RAM; 256 EEPROM; 25 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2320-I/SP

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 8K Bytes
• Ram Size: 512 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

TABLE 3-3:
 2003 Microchip Technology Inc.
Primary System
Clock
(PRI_IDLE mode)
T1OSC or
INTRC
INTOSC
Sleep mode
Note 1:
Clock in Power
Managed Mode
2:
3:
4:
5:
(1)
(2)
In this instance, refers specifically to the INTRC clock source.
Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
Two-Speed Start-up is covered in greater detail in Section 23.3 “Two-Speed Start-up”.
Execution continues during the INTOSC stabilization period.
Required delay when waking from Sleep and all Idle modes. This delay runs concurrently with any other
required delays (see Section 3.3 “Idle Modes”).
ACTIVITY AND EXIT DELAY ON WAKE-UP FROM SLEEP MODE OR
ANY IDLE MODE (BY CLOCK SOURCES)
LP, XT, HS
HSPLL
EC, RC, INTRC
INTOSC
LP, XT, HS
HSPLL
EC, RC, INTRC
INTOSC
LP, XT, HS
HSPLL
EC, RC, INTRC
INTOSC
LP, XT, HS
HSPLL
EC, RC, INTRC
INTOSC
Primary System
Clock
(2)
(2)
(2)
(2)
(1)
(1)
(1)
(1)
OST + 2 ms
OST + 2 ms
OST + 2 ms
Mode Exit
Managed
5-10 s
5-10 s
5-10 s
5-10 s
1 ms
1 ms
Power
Delay
None
OST
OST
OST
PIC18F2220/2320/4220/4320
(4)
(4)
(5)
(5)
(5)
(5)
Clock Ready
(OSCCON)
Status Bit
OSTS
OSTS
OSTS
OSTS
IOFS
IOFS
IOFS
IOFS
—
—
—
—
CPU and peripherals
clocked by primary clock
and executing
instructions.
CPU and peripherals
clocked by selected
power managed mode
clock and executing
instructions until primary
clock source becomes
ready.
Not clocked or
Two-Speed Start-up (if
enabled) until primary
clock source becomes
ready
Exit by Interrupt
(3)
.
Activity During Wake-up from
Power Managed Mode
Not clocked or
Two-Speed Start-up
(if enabled)
Exit by Reset
DS39599C-page 39
(3)
.