PIC18F2320-I/SP Microchip Technology Inc., PIC18F2320-I/SP Datasheet - Page 163

• Manufacturer Part Number: PIC18F2320-I/SP
• Description: Microcontroller; 8 KB Flash; 512 RAM; 256 EEPROM; 25 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2320-I/SP

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 8K Bytes
• Ram Size: 512 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

17.3.6
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in power managed modes, the slave can trans-
mit/receive data. When a byte is received, the device
will wake-up from power managed modes.
17.3.7
The SS pin allows a master controller to select one of
several slave controllers for communications in sys-
tems with more than one slave. The SPI must be in
Slave
(SSPCON1<3:0> = 04h). The SS pin is configured for
input by setting TRISA<5>. When the SS pin is low,
transmission and reception are enabled and the SDO
pin is driven. When the SS pin goes high, the SDO pin
FIGURE 17-4:
 2003 Microchip Technology Inc.
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
mode
SLAVE MODE
SLAVE SELECT CONTROL
with
SLAVE SYNCHRONIZATION WAVEFORM
SS
pin
bit 7
bit 7
control
bit 6
PIC18F2220/2320/4220/4320
enabled
is tri-stated, even if in the middle of a transmitted byte.
External pull-up/pull-down resistors may be desirable,
depending on the application.
When the SPI module resets, SSPSR is cleared. This
can be done by either driving the SS pin to a high level
or clearing the SSPEN bit.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver the SDO pin can be configured as
an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
Note 1: When the SPI is in Slave mode with SS pin
2: If the SPI is used in Slave mode with CKE
control enabled (SSPCON1<3:0> = 0100),
the SPI module will reset when the SS pin is
set high.
set, then the SS pin control must be
enabled.
bit 7
bit 7
Next Q4 Cycle
after Q2
DS39599C-page 161
bit 0
bit 0