PIC18F2320-I/SP Microchip Technology Inc., PIC18F2320-I/SP Datasheet - Page 37

• Manufacturer Part Number: PIC18F2320-I/SP
• Description: Microcontroller; 8 KB Flash; 512 RAM; 256 EEPROM; 25 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2320-I/SP

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 8K Bytes
• Ram Size: 512 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

3.3.3
In RC_IDLE mode, the CPU is disabled but the periph-
erals continue to be clocked from the internal oscillator
block using the INTOSC multiplexer. This mode allows
for controllable power conservation during Idle periods.
This mode is entered by setting the IDLEN bit, setting
SCS1 (SCS0 is ignored) and executing a SLEEP
instruction. The INTOSC multiplexer may be used to
select a higher clock frequency by modifying the IRCF
bits before executing the SLEEP instruction. When the
clock source is switched to the INTOSC multiplexer
(see Figure 3-7), the primary oscillator is shut down
and the OSTS bit is cleared.
If the IRCF bits are set to a non-zero value (thus
enabling the INTOSC output), the IOFS bit becomes
set after the INTOSC output becomes stable, in about
1 ms. Clocks to the peripherals continue while the
INTOSC source stabilizes. If the IRCF bits were previ-
ously at a non-zero value before the SLEEP instruction
FIGURE 3-7:
FIGURE 3-8:
 2003 Microchip Technology Inc.
INTRC
OSC1
CPU
Clock
Peripheral
Clock
Program
Counter
Multiplexer
CPU Clock
Peripheral
Note 1: T
PLL Clock
Program
INTOSC
Counter
Output
OSC1
Clock
Q1
RC_IDLE MODE
Wake-up from Interrupt Event
OST
Q2
PC
= 1024 T
Q3
PC
Q4
Q4
TIMING TRANSITION TO RC_IDLE MODE
TIMING TRANSITION FOR WAKE FROM RC_RUN MODE (RC_RUN TO PRI_RUN)
OSC
Q1
; T
Q1
PLL
1
T
= 2 ms (approx). These intervals are not shown to scale.
OST
2
(1)
Q2
PC + 2
3
Clock Transition
T
OSTS bit Set
Q3
PLL (1)
PIC18F2220/2320/4220/4320
4
Q4
5
PC + 2
6
Q1
1
2
7
was executed and the INTOSC source was already
stable, the IOFS bit will remain set. If the IRCF bits are
all clear, the INTOSC output is not enabled and the
IOFS bit will remain clear; there will be no indication of
the current clock source.
When a wake-up event occurs, the peripherals con-
tinue to be clocked from the INTOSC multiplexer. After
a 10 s delay following the wake-up event, the CPU
begins executing code, being clocked by the INTOSC
multiplexer. The microcontroller operates in RC_RUN
mode until the primary clock becomes ready. When the
primary clock becomes ready, a clock switch back to
the primary clock occurs (see Figure 3-8). When the
clock switch is complete, the IOFS bit is cleared, the
OSTS bit is set and the primary clock is providing the
system clock. The IDLEN and SCS bits are not affected
by the wake-up. The INTRC source will continue to run
if either the WDT or the Fail-Safe Clock Monitor is
enabled.
Clock Transition
3
8
4
5
PC + 4
6
7
8
Q2
Q3 Q4
DS39599C-page 35
Q1
PC + 6
Q2
Q3