PIC18F2320-I/SP Microchip Technology Inc., PIC18F2320-I/SP Datasheet - Page 147

• Manufacturer Part Number: PIC18F2320-I/SP
• Description: Microcontroller; 8 KB Flash; 512 RAM; 256 EEPROM; 25 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2320-I/SP

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 8K Bytes
• Ram Size: 512 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

16.4.2
In the Half-Bridge Output mode, two pins are used as
outputs to drive push-pull loads. The PWM output sig-
nal is output on the RC2/CCP1/P1A pin, while the com-
plementary PWM output signal is output on the RD5/
PSP5/P1B pin (Figure 16-4). This mode can be used
for half-bridge applications, as shown in Figure 16-5, or
for full-bridge applications where four power switches
are being modulated with two PWM signals.
In Half-Bridge Output mode, the programmable dead
band delay can be used to prevent shoot-through
current in half-bridge power devices. The value of bits
PDC6:PDC0 sets the number of instruction cycles
before the output is driven active. If the value is greater
than the duty cycle, the corresponding output remains
inactive during the entire cycle. See Section 16.4.4
“Programmable Dead Band Delay” for more details
of the dead band delay operations.
Since the P1A and P1B outputs are multiplexed with
the PORTC<2> and PORTD<5> data latches, the
TRISC<2> and TRISD<5> bits must be cleared to
configure P1A and P1B as outputs.
FIGURE 16-5:
 2003 Microchip Technology Inc.
Standard Half-Bridge Circuit (“Push-Pull”)
Half-Bridge Output Driving a Full-Bridge Circuit
HALF-BRIDGE MODE
EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS
PIC18F4220/4320
P1A
P1B
PIC18F4220/4320
PIC18F2220/2320/4220/4320
P1A
P1B
FET
Driver
FET
Driver
FET
Driver
FET
Driver
FIGURE 16-4:
Note 1: At this time, the TMR2 register is equal to the PR2
P1A
P1B
td = Dead Band Delay
(2)
(2)
2: Output signals are shown as active-high.
Load
(1)
register.
V+
V-
V+
V-
Duty Cycle
td
Period
Load
td
HALF-BRIDGE PWM
OUTPUT
FET
Driver
FET
Driver
(1)
+
V
-
+
V
-
DS39599C-page 145
Period
(1)