PIC18F2320-I/SP Microchip Technology Inc., PIC18F2320-I/SP Datasheet - Page 138

• Manufacturer Part Number: PIC18F2320-I/SP
• Description: Microcontroller; 8 KB Flash; 512 RAM; 256 EEPROM; 25 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2320-I/SP

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 8K Bytes
• Ram Size: 512 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2220/2320/4220/4320
15.4
In Compare mode, the 16-bit CCPR1 (CCPR2) register
value is constantly compared against either the
TMR1 register pair value, or the TMR3 register pair
value. When a match occurs, the RC2/CCP1/P1A
(RC1/T1OSI/CCP2) pin:
• Is driven High
• Is driven Low
• Toggles output (High to Low or Low to High)
• Remains unchanged (interrupt only)
The action on the pin is based on the value of control
bits, CCP1M3:CCP1M0 (CCP2M3:CCP2M0). At the
same time, interrupt flag bit, CCP1IF (CCP2IF), is set.
15.4.1
The user must configure the CCPx pin as an output by
clearing the appropriate TRISC bit.
FIGURE 15-2:
DS39599C-page 136
Note:
RC1/T1OSI/CCP2
Special Event Trigger will:
RC2/CCP1/P1A
Reset Timer1 or Timer3 but not set Timer1 or Timer3 interrupt flag bit
and set bit GO/DONE (ADCON0<2>) which starts an A/D conversion (CCP2 only)
pin
Compare Mode
pin
CCP PIN CONFIGURATION
Clearing the CCP1CON register will force
the RC2/CCP1/P1A compare output latch
to the default low level. This is not the
PORTC I/O data latch.
Output Enable
Output Enable
TRISC<2>
TRISC<1>
COMPARE MODE OPERATION BLOCK DIAGRAM
Q
Q
R
R
S
S
Special Event Trigger
Special Event Trigger
CCP1CON<3:0>
CCP2CON<3:0>
Mode Select
Mode Select
Output
Output
Logic
Logic
Set Flag bit CCP1IF
Set Flag bit CCP2IF
Match
Match
15.4.2
Timer1 and/or Timer3 must be running in Timer mode,
or Synchronized Counter mode, if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
15.4.3
When generate software interrupt is chosen, the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
15.4.4
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
The special trigger output of CCP2 resets either the
TMR1 or TMR3 register pair. Additionally, the CCP2
special event trigger will start an A/D conversion if the
A/D module is enabled.
Note:
T3CCP1
T3CCP2
TMR1H
TIMER1/TIMER3 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
The special event trigger from the CCP2
module will not set the Timer1 or Timer3
interrupt flag bits.
T3CCP2
TMR1L
CCPR1H CCPR1L
CCPR2H CCPR2L
 2003 Microchip Technology Inc.
Comparator
Comparator
0
0
1
1
TMR3H
TMR3L