PIC18F2320-I/SP Microchip Technology Inc., PIC18F2320-I/SP Datasheet - Page 183

• Manufacturer Part Number: PIC18F2320-I/SP
• Description: Microcontroller; 8 KB Flash; 512 RAM; 256 EEPROM; 25 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2320-I/SP

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 8K Bytes
• Ram Size: 512 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

17.4.7
In I
reload value is placed in the lower 7 bits of the
SSPADD register (Figure 17-17). When a write occurs
to SSPBUF, the Baud Rate Generator will automatically
begin counting. The BRG counts down to ‘0’ and stops
until another reload has taken place. The BRG count is
decremented twice per instruction cycle (T
Q2 and Q4 clocks. In I
reloaded automatically.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
Table 17-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
FIGURE 17-17:
TABLE 17-3:
 2003 Microchip Technology Inc.
Note 1:
2
C Master mode, the Baud Rate Generator (BRG)
40 MHz
40 MHz
40 MHz
16 MHz
16 MHz
16 MHz
4 MHz
4 MHz
4 MHz
F
2:
OSC
The I
100 kHz) in all details, but may be used with care where higher rates are required by the application.
Actual clock rate will depend on bus conditions. Bus capacitance can increase rise time and extend the low
time of the clock period, reducing the effective clock frequency (see Section 17.4.7.2 “Clock Arbitration”).
BAUD RATE
2
C interface does not conform to the 400 kHz I
I
2
C CLOCK RATE W/BRG
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM3:SSPM0
2
10 MHz
10 MHz
10 MHz
C Master mode, the BRG is
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
1 MHz
F
CY
SCL
SSPM3:SSPM0
20 MHz
20 MHz
20 MHz
CY
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
2 MHz
F
PIC18F2220/2320/4220/4320
CY
) on the
Reload
Control
*2
CLKO
Reload
(See Register 17-4,
SSPADD VALUE
17.4.7.1
When the device is operating in a power managed
mode, the clock source to the Baud Rate Generator
may change frequency or stop, depending on the
power managed mode and clock source selected.
In most power modes, the Baud Rate Generator
continues to be clocked but may be clocked from the
primary clock (selected in a configuration word), the
secondary clock (Timer1 oscillator at 32.768 kHz) or
the internal oscillator block (one of eight frequencies
between
selected, all clocks are stopped and the Baud Rate
Generator will not be clocked.
2
BRG Down Counter
C specification (which applies to rates greater than
Mode 1000)
SSPADD<6:0>
1Fh
0Bh
18h
63h
09h
27h
02h
09h
00h
31 kHz and 8 MHz). If the Sleep mode is
Baud Rate Generation in Power
Managed Modes
F
OSC
(2 Rollovers of BRG)
/4
400 kHz
400 kHz
333 kHz
312.5 kHz
1 MHz
100 kHz
308 kHz
100 kHz
100kHz
DS39599C-page 181
F
SCL
(2)
(1)
(1)
(1)
(1)