PIC16F785-I/P Microchip Technology Inc., PIC16F785-I/P Datasheet - Page 91

• Manufacturer Part Number: PIC16F785-I/P
• Description: MCU, 8-Bit, 2KW Flash, 128 RAM, 18 I/O, DIP-20
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F785-I/P

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 17
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 20-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

12.4
A device Reset forces all registers to their Reset state.
Thus, the A/D module is turned off and any pending
conversion
registers are unchanged.
12.5
An A/D conversion can be started by the “special event
trigger” of the CCP module. This requires that the
CCP1M3:CCP1M0
programmed as ‘1011’ and that the A/D module is
enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D conversion
and the Timer1 counter will be reset to zero. Timer1 is
reset to automatically repeat the A/D acquisition period
with
ADRESH:ADRESL to the desired location).
TABLE 12-3:
© 2006 Microchip Technology Inc.
05h,105h
06h,106h
07h,107h
0Bh,8Bh,
10Bh,18Bh
0Ch
1Eh
1Fh
85h,185h
86h,186h
87h,187h
8Ch
91h
93h
9Eh
9Fh
Legend:
Addr
minimal
Effects of Reset
Use of the CCP Trigger
PORTA
PORTB
PORTC
INTCON
PIR1
ADRESH
ADCON0
TRISA
TRISB
TRISC
PIE1
ANSEL0
ANSEL1
ADRESL
ADCON1
x = unknown, u = unchanged, – = unimplemented read as ‘0’. Shaded cells are not used for A/D module.
Name
is
software
aborted.
SUMMARY OF A/D REGISTERS
Most Significant 8 bits of the left justified A/D result or 2 bits of the right justified result
Least Significant 2 bits of the left justified A/D result or 8 bits of the right justified result
TRISC7
TRISB7
ADFM
ANS7
Bit 7
EEIF
EEIE
RC7
RB7
GIE
bits
—
—
—
—
overhead
The
(CCP1CON<3:0>)
TRISB6
TRISC6
ADCS2
VCFG
ANS6
PEIE
ADIF
ADIE
Bit 6
RB6
RC6
—
—
—
ADRESH:ADRESL
CCP1IE
CCP1IF
TRISA5
TRISB5
TRISC5
ADCS1
CHS3
ANS5
Bit 5
RC5
T0IE
RA5
RB5
(moving
—
TRISA4
TRISB4
TRISC4
ADCS0
CHS2
ANS4
INTE
Bit 4
C2IF
C2IE
RA4
RB4
RC4
—
Preliminary
the
be
TRISA3
TRISC3
ANS11
CHS1
ANS3
Bit 3
RAIE
C1IE
C1IF
RA3
RC3
—
—
—
The appropriate analog input channel must be selected
and the minimum acquisition done before the “special
event trigger” sets the GO/DONE bit (starts a
conversion).
If the A/D module is not enabled (ADON is cleared), then
the “special event trigger” will be ignored by the
module, but will still reset the Timer1 counter. See
Section 8.0 “Capture/Compare/PWM (CCP) Module”
for more information.
TRISA2
TRISC2
ANS10
OSFIE
OSFIF
CHS0
ANS2
Bit 2
RC2
T0IF
RA2
—
—
—
PIC16F785/HV785
GO/DONE
TMR2IF
TRISA1
TRISC1
TMR2IE
ANS1
ANS9
Bit 1
INTF
RA1
RC1
—
—
—
TMR1IF
TRISC0
TMR1IE
TRISA0
ADON
ANS0
ANS8
Bit 0
RAIF
RC0
RA0
—
—
—
--xx xxxx
xxxx ----
xxxx xxxx
0000 0000
0000 0000
xxxx xxxx
0000 0000
--11 1111
1111 ----
1111 1111
0000 0000
1111 1111
---- 1111
xxxx xxxx
-000 ----
POR, BOR
Value on:
DS41249D-page 89
--uu uuuu
uuuu ----
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
--11 1111
1111 ----
1111 1111
0000 0000
1111 1111
---- 1111
uuuu uuuu
-000 ----
Value on
all other
Resets
A/D