PIC16F785-I/P Microchip Technology Inc., PIC16F785-I/P Datasheet - Page 114

• Manufacturer Part Number: PIC16F785-I/P
• Description: MCU, 8-Bit, 2KW Flash, 128 RAM, 18 I/O, DIP-20
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F785-I/P

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 17
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 20-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F785/HV785
15.2.6
On power-up, the time-out sequence is as follows: first,
PWRT time out is invoked after POR has expired, then
OST is activated after the PWRT time out has expired.
The total time out will vary based on oscillator configu-
ration and PWRTE bit status. For example, in EC mode
with PWRTE bit equal to ‘1’ (PWRT disabled), there will
be no time out at all. Figure 15-4, Figure 15-6 and
Figure 15-6 depict time-out sequences. The device can
execute code from the INTOSC, while OST is active by
enabling Two-Speed Start-up or Fail-Safe Monitor (see
Section 3.6.2 “Two-Speed Start-up Sequence” and
Section 3.7 “Fail-Safe Clock Monitor”).
Since the time outs occur from the POR pulse, if MCLR
is kept low long enough, the time outs will expire. Then
bringing MCLR high will begin execution immediately
(see Figure 15-6). This is useful for testing purposes or
to synchronize more than one PIC16F785/HV785
device operating in parallel.
Table 15-5 shows the Reset conditions for some
special registers, while Table 15-4 shows the Reset
conditions for all the registers.
TABLE 15-1:
TABLE 15-2:
TABLE 15-3:
DS41249D-page 112
03h, 103h
83h, 183h
8Eh
Legend:
Note 1:
Legend: u = unchanged, x = unknown
Address
Oscillator Configuration
POR
0
u
u
u
u
u
RC, EC, INTOSC
XT, HS, LP
STATUS
PCON
u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Shaded cells are not
used by BOR.
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
TIME-OUT SEQUENCE
Name
BOR
x
0
u
u
u
u
TIME OUT IN VARIOUS SITUATIONS
STATUS/PCON BITS AND THEIR SIGNIFICANCE
SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT
Bit 7
IRP
—
TO
1
1
0
0
u
1
Bit 6
RP1
—
PWRTE = 0
1024•T
T
T
PWRT
PD
PWRT
1
1
u
0
u
0
Bit 5
RP0
—
OSC
+
Power-up
Power-on Reset
Brown-out Reset
WDT Reset
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during Sleep
SBOREN
Bit 4
TO
PWRTE = 1
Preliminary
1024•T
—
OSC
Bit 3
PD
—
15.2.7
The Power Control register (address 8Eh) has two Sta-
tus bits to indicate what type of Reset that last
occurred.
Bit 0 is BOR (Brown-out Reset). BOR is unknown on
Power-on Reset. It must then be set by the user and
checked on subsequent Resets to see if BOR = 0,
indicating that a Brown-out has occurred. The BOR
Status bit is a “don’t care” and is not necessarily
predictable if the brown-out circuit is disabled
(BOREN<1:0> = 00 in the Configuration Word).
Bit 1 is POR (Power-on Reset). It is ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a
subsequent Reset, if POR is ‘0’, it will indicate that a
Power-on Reset has occurred (i.e., V
gone too low).
For more information, see Section 15.2.4 “Brown-Out
Reset (BOR)”.
Bit 2
—
PWRTE = 0
Z
1024•T
T
T
PWRT
PWRT
Brown-out Reset
POWER CONTROL (PCON)
REGISTER
Condition
Bit 1
POR
OSC
DC
+
Bit 0
BOR
C
PWRTE = 1
1024•T
© 2006 Microchip Technology Inc.
—
0001 1xxx
---1 --qq
POR, BOR
Value on:
OSC
Wake-up from
DD
1024•T
Value on all
000q quuu
---u --uu
Sleep
Resets
may have
—
other
OSC
(1)