PIC16F785-I/P Microchip Technology Inc., PIC16F785-I/P Datasheet - Page 33

• Manufacturer Part Number: PIC16F785-I/P
• Description: MCU, 8-Bit, 2KW Flash, 128 RAM, 18 I/O, DIP-20
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F785-I/P

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 17
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 20-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

FIGURE 3-7:
3.7
The Fail-Safe Clock Monitor (FSCM) is designed to
allow the device to continue to operate in the event of
an oscillator failure. The FSCM can detect oscillator
failure at any point after the device has exited a Reset
or Sleep condition and the Oscillator Start-up Timer
(OST) has expired.
FIGURE 3-8:
The FSCM function is enabled by setting the FCMEN
bit in Configuration Word (CONFIG). It is applicable to
all external clock options (LP, XT, HS, EC, RC or I/O
modes).
In the event of an external clock failure, the FSCM will
set the OSFIF bit (PIR1<2>) and generate an oscillator
fail interrupt if the OSFIE bit (PIE1<2>) is set. The
device will then switch the system clock to the internal
oscillator. The system clock will continue to come from
the internal oscillator unless the external clock recovers
and the Fail-Safe condition is exited.
© 2006 Microchip Technology Inc.
Program Counter
LFINTOSC
Oscillator
(~32 s)
Primary
31 kHz
Clock
System Clock
Fail-Safe Clock Monitor
INTOSC
OSC1
OSC2
(~2 ms)
488 Hz
÷ 64
TWO-SPEED START-UP
Q1
FSCM BLOCK DIAGRAM
0
(edge-triggered)
Clock Monitor
Q2
Latch (CM)
C
S
1
T
T
OST
Q3
Q
Q
1022 1023
PC
Q4
Detected
Failure
Clock
Preliminary
Q1
Q2
The frequency of the internal oscillator will depend
upon
(OSCCON<6:4>). Upon entering the Fail-Safe condi-
tion, the OSTS bit (OSCCON<3>) is automatically
cleared to reflect that the internal oscillator is active and
the WDT is cleared. The SCS bit (OSCCON<0>) is not
updated. Enabling FSCM does not affect the LTS bit.
The FSCM sample clock is generated by dividing the
LFINTOSC clock by 64. This will allow enough time
between FSCM sample clocks for a system clock edge
to occur. Figure 3-8 shows the FSCM block diagram.
On the rising edge of the sample clock, the monitoring
latch (CM = 0) will be cleared. On a falling edge of the
primary system clock, the monitoring latch will be set
(CM = 1). In the event that a falling edge of the sample
clock occurs, and the monitoring latch is not set, a clock
failure has been detected. The assigned internal
oscillator is enabled when FSCM is enabled as
reflected by the IRCF bits.
Note:
the
PC + 1
PIC16F785/HV785
Two-Speed
enabled when the Fail-Safe Clock Monitor
mode is enabled.
value
Q3
contained
Start-up
Q4
in
is
DS41249D-page 31
the
PC + 2
automatically
Q1
IRCF
bits