PIC16F785-I/P Microchip Technology Inc., PIC16F785-I/P Datasheet - Page 52

• Manufacturer Part Number: PIC16F785-I/P
• Description: MCU, 8-Bit, 2KW Flash, 128 RAM, 18 I/O, DIP-20
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F785-I/P

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 17
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 20-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F785/HV785
5.3
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI, with the internal phase clocks, is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2T
a small RC delay of 20 ns) and low for at least 2T
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
5.4
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer. For simplicity, this counter will be referred to as
“prescaler” throughout this Data Sheet. The prescaler
assignment is controlled in software by the control bit
PSA (OPTION_REG<3>). Clearing the PSA bit will
assign the prescaler to Timer0. Prescale values are
selectable via the PS<2:0> bits (OPTION_REG<2:0>).
The prescaler is not readable or writable. When
assigned to the Timer0 module, all instructions writing
to the TMR0 register (e.g., CLRF 1,
BSF 1,x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer.
TABLE 5-1:
DS41249D-page 50
01h,
101h
0Bh,
8Bh
81h,
181h
91h
85h,
185h
Legend:
Addr
ANSEL0
TMR0
INTCON
OPTION_REG
TRISA
Using Timer0 with an External
Clock
Prescaler
module.
Name
– = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Timer0
REGISTERS ASSOCIATED WITH TIMER0
Timer0 Module Register
RAPU
ANS7
Bit 7
GIE
—
INTEDG
ANS6
Bit 6
PEIE
—
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
ANS5
T0CS
Bit 5
T0IE
MOVWF 1,
OSC
(and
OSC
ANS4
T0SE
Preliminary
INTE
Bit 4
ANS3
RAIE
Bit 3
PSA
5.4.1
The prescaler assignment is fully under software
control (i.e., it can be changed “on the fly” during
program execution). To avoid an unintended device
Reset, the following instruction sequence (Example 5-
1 and Example 5-2) must be executed when changing
the prescaler assignment between Timer0 and WDT.
EXAMPLE 5-1:
To change prescaler from the WDT to the TMR0
module, use the sequence shown in Example 5-2. This
precaution must be taken even if the WDT is disabled.
EXAMPLE 5-2:
BCF
BCF
CLRWDT
CLRF
BSF
MOVLW
MOVWF
CLRWDT
MOVLW
MOVWF
BCF
CLRWDT
BSF
BCF
MOVLW
MOVWF
BCF
ANS2
Bit 2
T0IF
PS2
STATUS,RP0
STATUS,RP1
TMR0
STATUS,RP0
b’00101111’
OPTION_REG
b’00101xxx’
OPTION_REG
STATUS,RP0
STATUS,RP0
STATUS,RP1
b’xxxx0xxx’
OPTION_REG
STATUS,RP0
SWITCHING PRESCALER
ASSIGNMENT
ANS1
Bit 1
INTF
PS1
ANS0
RAIF
CHANGING PRESCALER
(TIMER0 WDT)
CHANGING PRESCALER
(WDT TIMER0)
Bit 0
PS0
© 2006 Microchip Technology Inc.
;Bank 0
;
;Clear WDT
;Clear TMR0 and
; prescaler
;Bank 1
;Required if desired
; PS2:PS0 is
; 000 or 001
;
;Set postscaler to
; desired WDT rate
;Bank 0
;Clear WDT and
; prescaler
;Bank 1
;
;Select TMR0,
; prescale, and
; clock source
;
;Bank 0
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1111
POR, BOR
Value on:
Value on
all other
Resets