PIC16F785-I/P Microchip Technology Inc., PIC16F785-I/P Datasheet - Page 11

• Manufacturer Part Number: PIC16F785-I/P
• Description: MCU, 8-Bit, 2KW Flash, 128 RAM, 18 I/O, DIP-20
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F785-I/P

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 17
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 20-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

2.0
2.1
The PIC16F785/HV785 has a 13-bit program counter
capable of addressing an 8k x 14 program memory
space. Only the first 2k x 14 (0000h-07FFh) for the
PIC16F785/HV785 is physically implemented. Access-
ing a location above these boundaries will cause a
wrap around within the first 2k x 14 space. The Reset
vector is at 0000h and the interrupt vector is at 0004h
(see Figure 2-1).
FIGURE 2-1:
© 2006 Microchip Technology Inc.
CALL, RETURN
RETFIE, RETLW
MEMORY ORGANIZATION
Program Memory Organization
On-chip Program
Interrupt Vector
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector
PC<12:0>
Memory
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16F785/HV785
13
000h
0004
0005
07FFh
0800h
1FFFh
Preliminary
2.2
The data memory (see Figure 2-2) is partitioned into
four banks, which contain the General Purpose Regis-
ters (GPR) and the Special Function Registers (SFR).
The Special Function Registers are located in the first
32 locations of each bank. Register locations 20h-7Fh
in Bank 0 and A0h-BFh in Bank 1 are General Purpose
Registers, implemented as static RAM. The last sixteen
register locations in Bank 1 (F0h-FFh), Bank 2 (170h-
17Fh), and Bank 3 (1F0h-1FFh) point to addresses
70h-7Fh in Bank 0. All other RAM is unimplemented
and returns ‘0’ when read.
Seven address bits are required to access any location
in a data memory bank. Two additional bits are required
to access the four banks. When data memory is
accessed directly, the seven Least Significant address
bits are contained within the opcode and the two Most
Significant bits are contained in the STATUS register.
RP0 and RP1 (STATUS<5> and STATUS<6>) are the
two Most Significant data memory address bits and are
also known as the bank select bits. Table 2-1 lists how
to access the four banks of registers.
TABLE 2-1:
2.2.1
The register file banks are organized as 128 x 8 in the
PIC16F785/HV785. Each register is accessed, either
directly, by seven address bits within the opcode, or
indirectly, through the File Select Register (FSR).
When the FSR is used to access data memory, the
eight Least Significant data memory address bits are
contained in the FSR and the ninth Most Significant
address bit is contained in the IRP bit (STATUS<7>) of
the STATUS register. (see Section 2.4 “Indirect
Addressing, INDF and FSR Registers”).
2.2.2
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Table 2-2). These
registers are static RAM.
The special registers can be classified into two sets:
core and peripheral. The Special Function Registers
associated with the “core” are described in this section.
Those related to the operation of the peripheral
features are described in the section of that peripheral
feature.
Bank 0
Bank 1
Bank 2
Bank 3
PIC16F785/HV785
Data Memory Organization
GENERAL PURPOSE REGISTER
FILE
SPECIAL FUNCTION REGISTERS
BANK SELECTION
RP1
0
0
1
1
DS41249D-page 9
RP0
0
1
0
1