PIC16F785-I/P Microchip Technology Inc., PIC16F785-I/P Datasheet - Page 62

• Manufacturer Part Number: PIC16F785-I/P
• Description: MCU, 8-Bit, 2KW Flash, 128 RAM, 18 I/O, DIP-20
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F785-I/P

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 17
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 20-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F785/HV785
8.3
In Pulse Width Modulation (PWM) mode, the CCP
module produces up to a 10-bit resolution PWM output
on the RC5/CCP1 pin. Since the RC5/CCP1 pin is
multiplexed with the PORTC data latch, the TRISC<5>
must be cleared to make the RC5/CCP1 pin an output.
Figure 8-3 shows a simplified block diagram of PWM
operation.
For a step by step procedure on how to set up the CCP
module for PWM operation, see Section 8.3.5 “Setup
for PWM Operation”.
FIGURE 8-3:
The PWM output (Figure 8-4) has a time base
(period) and a time that the output stays high (duty
cycle). The frequency of the PWM is the inverse of
the period (1/period).
FIGURE 8-4:
DS41249D-page 60
Note 1:
Note:
CCPR1H (Slave)
Duty Cycle Registers
Comparator
Duty Cycle
CCP PWM Mode
CCPR1L
TMR2 = 0
PR2
TMR2
Comparator
Clearing the CCP1CON register will force
the PWM output latch to the default
inactive levels. This is not the PORTC I/O
data latch.
The 8-bit timer TMR2 register is concate-
nated with the 2-bit internal Q clock, or 2 bits
of the prescaler, to create the 10-bit time
base.
Period
(1)
SIMPLIFIED PWM BLOCK
DIAGRAM
CCP PWM OUTPUT
Clear Timer2,
toggle PWM pin and
latch duty cycle
TMR2 = Duty Cycle
CCP1CON<5:4>
TMR2 = PR2
S
R
Q
TRISC<5>
RC5/CCP1
Preliminary
8.3.1
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
formula of Equation 8-1.
EQUATION 8-1:
PWM frequency is defined as 1/[PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The RC5/CCP1 pin is set. (exception: if PWM
• The PWM duty cycle is latched from CCPR1L into
duty cycle = 0%, the pin will not be set)
CCPR1H
Note:
PWM period
PWM PERIOD
The Timer2 postscaler (see Section 7.1
“Timer2 Operation”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
=
(TMR2 prescale value)
PWM PERIOD
PR2
© 2006 Microchip Technology Inc.
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