PIC17C756A-33/L Microchip Technology Inc., PIC17C756A-33/L Datasheet - Page 67

• Manufacturer Part Number: PIC17C756A-33/L
• Description: 68 PIN, 32 KB OTP, 902 RAM, 50 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC17C756A-33/L

• A/d Inputs: 12-Channel, 10-Bit
• Cpu Speed: 8.25 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/USART
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 32K Bytes
• Ram Size: 902 Bytes
• Speed: 16 MHz
• Timers: 2-8-bit, 2-16-bit
• Voltage, Range: 3-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

9.0
All PIC17C7XX devices have an 8 x 8 hardware multi-
plier included in the ALU of the device. By making the
multiply a hardware operation, it completes in a single
instruction cycle. This is an unsigned multiply that gives
a 16-bit result. The result is stored into the 16-bit
Product register (PRODH:PRODL). The multiplier does
not affect any flags in the ALUSTA register.
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
• Higher computational throughput
• Reduces code size requirements for multiply algo-
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
Table 9-1 shows a performance comparison between
PIC17CXXX devices using the single cycle hardware
multiply and performing the same function without the
hardware multiply.
Example 9-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
TABLE 9-1:
8 x 8 unsigned
8 x 8 signed
16 x 16 unsigned
16 x 16 signed
rithms
2000 Microchip Technology Inc.
Routine
HARDWARE MULTIPLIER
PERFORMANCE COMPARISON
Without hardware multiply
Hardware multiply
Without hardware multiply
Hardware multiply
Without hardware multiply
Hardware multiply
Without hardware multiply
Hardware multiply
Multiply Method
Program
Memory
(Words)
13
21
24
52
36
—
1
6
Example 9-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s most significant bit (MSb) is tested
and the appropriate subtractions are done.
EXAMPLE 9-1:
EXAMPLE 9-2:
Cycles
(Max)
MOVFP
MULWF
MOVFP
MULWF
BTFSC
SUBWF
MOVFP
BTFSC
SUBWF
242
254
69
24
36
—
1
6
@ 33 MHz
ARG1, WREG
ARG2
ARG1, WREG
ARG2
ARG2, SB
PRODH, F
ARG2, WREG
ARG1, SB
PRODH, F
29.333 s
30.788 s
8.364 s
0.121 s
0.727 s
2.91 s
4.36 s
—
8 x 8 UNSIGNED
MULTIPLY ROUTINE
8 x 8 SIGNED MULTIPLY
ROUTINE
PIC17C7XX
@ 16 MHz
17.25 s
60.50 s
63.50 s
;
; ARG1 * ARG2 ->
;
; ARG1 * ARG2 ->
;
; Test Sign Bit
; PRODH = PRODH
;
; Test Sign Bit
; PRODH = PRODH
;
0.25 s
1.50 s
Time
6.0 s
9.0 s
—
DS30289B-page 67
PRODH:PRODL
PRODH:PRODL
@ 8 MHz
34.50 s
121.0 s
127.0 s
- ARG1
- ARG2
0.50 s
12.0 s
18.0 s
3.0 s
—