PIC17C756A-33/L Microchip Technology Inc., PIC17C756A-33/L Datasheet - Page 201

• Manufacturer Part Number: PIC17C756A-33/L
• Description: 68 PIN, 32 KB OTP, 902 RAM, 50 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC17C756A-33/L

• A/d Inputs: 12-Channel, 10-Bit
• Cpu Speed: 8.25 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/USART
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 32K Bytes
• Ram Size: 902 Bytes
• Speed: 16 MHz
• Timers: 2-8-bit, 2-16-bit
• Voltage, Range: 3-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

TABLE 18-2:
Mnemonic,
Operands
TSTFSZ
XORWF
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
BTG
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
LCALL
MOVLB
MOVLR
MOVLW
MULLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
Legend: Refer to Table 18-1 for opcode field descriptions.
Note 1: 2’s Complement method.
2000 Microchip Technology Inc.
2: Unsigned arithmetic.
3: If s = '1', only the file is affected: If s = '0', both the WREG register and the file are affected; If only the Working register
4: During an LCALL, the contents of PCLATH are loaded into the MSB of the PC and kkkk kkkk is loaded into the LSB of the
5: Multiple cycle instruction for EPROM programming when table pointer selects internal EPROM. The instruction is termi-
6: Two-cycle instruction when condition is true, else single cycle instruction.
7: Two-cycle instruction except for TABLRD to PCL (program counter low byte), in which case it takes 3 cycles.
8: A “skip” means that instruction fetched during execution of current instruction is not executed, instead a NOP is executed.
(WREG) is required to be affected, then f = WREG must be specified.
PC (PCL).
nated by an interrupt event. When writing to external program memory, it is a two-cycle instruction.
f
f,d
f,b
f,b
f,b
f,b
f,b
k
k
k
—
k
k
k
k
k
k
k
—
k
—
—
k
k
PIC17CXXX INSTRUCTION SET (CONTINUED)
Description
Test f, skip if 0
Exclusive OR WREG with f
Bit Clear f
Bit Set f
Bit test, skip if clear
Bit test, skip if set
Bit Toggle f
ADD literal to WREG
AND literal with WREG
Subroutine Call
Clear Watchdog Timer
Unconditional Branch
Inclusive OR literal with WREG
Long Call
Move literal to low nibble in BSR
Move literal to high nibble in BSR
Move literal to WREG
Multiply literal with WREG
Return from interrupt (and enable interrupts)
Return literal to WREG
Return from subroutine
Enter SLEEP mode
Subtract WREG from literal
Exclusive OR literal with WREG
Cycles
1 (2)
1 (2)
1 (2)
1
1
1
1
1
1
2
1
2
1
2
1
1
1
1
2
2
2
1
1
1
0011
0000
1000
1000
1001
1001
0011
1011
1011
111k
0000
110k
1011
1011
1011
1011
1011
1011
0000
1011
0000
0000
1011
1011
MSb
16-bit Opcode
0011 ffff ffff
110d ffff ffff
1bbb ffff ffff
0bbb ffff ffff
1bbb ffff ffff
0bbb ffff ffff
1bbb ffff ffff
0001 kkkk kkkk
0101 kkkk kkkk
kkkk kkkk kkkk
0000 0000 0100
kkkk kkkk kkkk
0011 kkkk kkkk
0111 kkkk kkkk
1000 uuuu kkkk
101x kkkk uuuu
0000 kkkk kkkk
1100 kkkk kkkk
0000 0000 0101
0110 kkkk kkkk
0000 0000 0010
0000 0000 0011
0010 kkkk kkkk
0100 kkkk kkkk
PIC17C7XX
LSb
Status
Affected
OV,C,DC,Z
OV,C,DC,Z
DS30289B-page 201
GLINTD
TO, PD
TO, PD
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Z
Z
Z
Z
Notes
6,8
6,8
6,8
4,7
7
7
7
7
7