PIC17C756A-33/L Microchip Technology Inc., PIC17C756A-33/L Datasheet - Page 120

• Manufacturer Part Number: PIC17C756A-33/L
• Description: 68 PIN, 32 KB OTP, 902 RAM, 50 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC17C756A-33/L

• A/d Inputs: 12-Channel, 10-Bit
• Cpu Speed: 8.25 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/USART
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 32K Bytes
• Ram Size: 902 Bytes
• Speed: 16 MHz
• Timers: 2-8-bit, 2-16-bit
• Voltage, Range: 3-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC17C7XX
14.1
The BRG supports both the Asynchronous and Syn-
chronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. Table 14-2 shows
the formula for computation of the baud rate for differ-
ent USART modes. These only apply when the USART
is in Synchronous Master mode (internal clock) and
Asynchronous mode.
Given the desired baud rate and Fosc, the nearest inte-
ger value between 0 and 255 can be calculated using
the formula below. The error in baud rate can then be
determined.
TABLE 14-2:
X = value in SPBRG (0 to 255)
Example 14-1 shows the calculation of the baud rate
error for the following conditions:
TABLE 14-3:
DS30289B-page 120
Legend:
SYNC
0
1
13h, Bank 0
15h, Bank 0
17h, Bank 0
13h, Bank 4
15h, Bank 4
17h, Bank 4
F
Desired Baud Rate = 9600
SYNC = 0
Address
OSC
USART Baud Rate Generator
(BRG)
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Baud Rate Generator.
Asynchronous
Synchronous
= 16 MHz
Mode
RCSTA1
TXSTA1
SPBRG1
RCSTA2
TXSTA2
SPBRG2
BAUD RATE FORMULA
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Name
Baud Rate Generator Register
Baud Rate Generator Register
CSRC
CSRC
SPEN
SPEN
Bit 7
F
F
OSC
OSC
Baud Rate
Bit 6
RX9
TX9
RX9
TX9
/(64(X+1))
/(4(X+1))
SREN
TXEN
SREN
TXEN
Bit 5
CREN
SYNC
CREN
SYNC
Bit 4
Bit 3
—
—
—
—
EXAMPLE 14-1:
Writing a new value to the SPBRG, causes the BRG
timer to be reset (or cleared). This ensures that the
BRG does not wait for a timer overflow before output-
ting the new baud rate.
Effects of Reset
After any device RESET, the SPBRG register is
cleared. The SPBRG register will need to be loaded
with the desired value after each RESET.
Desired Baud Rate = F
Calculated Baud Rate = 16000000 / (64 (25 + 1))
FERR
FERR
Bit 2
9600 = 16000000 /(64 (X + 1))
X
Error = (Calculated Baud Rate - Desired Baud Rate)
—
—
= 25.042
= 9615
= (9615 - 9600) / 9600
= 0.16%
OERR
TRMT
OERR
TRMT
Bit 1
OSC
RX9D
TX9D
RX9D
TX9D
Bit 0
CALCULATING BAUD
RATE ERROR
25
/ (64 (X + 1))
2000 Microchip Technology Inc.
Desired Baud Rate
0000 -00x
0000 --1x
0000 0000
0000 -00x
0000 --1x
0000 0000
Value on
POR,
BOR
MCLR, WDT
0000 -00u
0000 --1u
0000 0000
0000 -00u
0000 --1u
0000 0000