PIC17C756A-33/L Microchip Technology Inc., PIC17C756A-33/L Datasheet - Page 209

• Manufacturer Part Number: PIC17C756A-33/L
• Description: 68 PIN, 32 KB OTP, 902 RAM, 50 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC17C756A-33/L

• A/d Inputs: 12-Channel, 10-Bit
• Cpu Speed: 8.25 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/USART
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 32K Bytes
• Ram Size: 902 Bytes
• Speed: 16 MHz
• Timers: 2-8-bit, 2-16-bit
• Voltage, Range: 3-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

CPFSEQ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If skip:
Example:
2000 Microchip Technology Inc.
Before Instruction
After Instruction
operation
Decode
PC Address
WREG
REG
If REG
If REG
Q1
Q1
No
PC
PC
register ’f’
operation
Compare f with WREG,
skip if f = WREG
[ label ] CPFSEQ
0
(f) – (WREG),
skip if (f) = (WREG)
(unsigned comparison)
None
Compares the contents of data memory
location ’f’ to the contents of WREG by
performing an unsigned subtraction.
If ’f’ = WREG, then the fetched instruc-
tion is discarded and a NOP is executed
instead, making this a two-cycle
instruction.
1
1 (2)
HERE
NEQUAL
EQUAL
Read
0011
Q2
Q2
No
=
=
=
=
=
=
f
255
HERE
?
?
WREG;
Address (EQUAL)
WREG;
Address (NEQUAL)
CPFSEQ REG
:
:
0001
operation
Process
Data
Q3
Q3
No
ffff
f
operation
operation
Q4
Q4
No
No
ffff
CPFSGT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If skip:
Example:
Before Instruction
After Instruction
operation
Decode
PC
WREG
If REG
If REG
Q1
Q1
No
PC
PC
register ’f’
operation
Compare f with WREG,
skip if f > WREG
[ label ] CPFSGT
0
(f)
skip if (f) > (WREG)
(unsigned comparison)
None
Compares the contents of data memory
location ’f’ to the contents of the WREG
by performing an unsigned subtraction.
If the contents of ’f’ are greater than the
contents of WREG, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction.
1
1 (2)
HERE
NGREATER
GREATER
Read
0011
Q2
Q2
No
=
=
>
=
£
f
=
PIC17C7XX
WREG),
255
Address (HERE)
?
WREG;
Address (GREATER)
WREG;
Address (NGREATER)
0010
CPFSGT REG
:
:
operation
Process
Data
Q3
Q3
No
DS30289B-page 209
ffff
f
operation
operation
Q4
Q4
No
No
ffff