PIC17C756A-33/L Microchip Technology Inc., PIC17C756A-33/L Datasheet - Page 25

• Manufacturer Part Number: PIC17C756A-33/L
• Description: 68 PIN, 32 KB OTP, 902 RAM, 50 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC17C756A-33/L

• A/d Inputs: 12-Channel, 10-Bit
• Cpu Speed: 8.25 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/USART
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 32K Bytes
• Ram Size: 902 Bytes
• Speed: 16 MHz
• Timers: 2-8-bit, 2-16-bit
• Voltage, Range: 3-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

5.1.4
On power-up, the time-out sequence is as follows: First,
the internal POR signal goes high when the POR trip
point is reached. If MCLR is high, then both the OST and
PWRT timers start. In general, the PWRT time-out is
longer, except with low frequency crystals/resonators.
The total time-out also varies based on oscillator config-
uration. Table 5-1 shows the times that are associated
with the oscillator configuration. Figure 5-5 and Figure 5-
6 display these time-out sequences.
TABLE 5-1:
TABLE 5-2:
TABLE 5-3:
Note 1: When BODEN is enabled, else the BOR status bit is unknown.
Power-on Reset
Brown-out Reset
MCLR Reset during normal operation
MCLR Reset during SLEEP
WDT Reset during normal operation
WDT Reset during SLEEP
Interrupt Wake-up from SLEEP GLINTD is set
Legend: u = unchanged, x = unknown, - = unimplemented, read as '0'
Note 1: On wake-up, this instruction is executed. The instruction at the appropriate interrupt vector is fetched and
2000 Microchip Technology Inc.
POR
0
1
1
1
1
1
0
0
x
Configuration
2: The OST is only active (on wake-up) when the oscillator is configured for XT or LF modes.
3: The Program Counter = 0; that is, the device branches to the RESET vector and places SFRs in WDT
4: When BODEN is enabled, else the BOR status bit is unknown.
Oscillator
EC, RC
XT, LF
then executed.
Reset states. This is different from the mid-range devices.
TIME-OUT SEQUENCE
BOR
0
1
1
1
1
0
0
0
x
(1)
TIME-OUT IN VARIOUS SITUATIONS
STATUS BITS AND THEIR SIGNIFICANCE
RESET CONDITION FOR THE PROGRAM COUNTER AND THE CPUSTA REGISTER
Event
TO
1
1
0
0
1
1
0
x
1
(3)
GLINTD is clear
PD
1
0
1
0
1
1
x
0
1
Greater of: 96 ms or 1024T
Greater of: 96 ms or 1024T
Power-on Reset
MCLR Reset during SLEEP or interrupt wake-up from SLEEP
WDT Reset during normal operation
WDT Wake-up during SLEEP
MCLR Reset during normal operation
Brown-out Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
CLRWDT instruction executed
POR, BOR
PCH:PCL
PC + 1
PC + 1
0000h
0000h
0000h
0000h
0000h
0000h
If the device voltage is not within electrical specification
at the end of a time-out, the MCLR/V
held low until the voltage is within the device specifica-
tion. The use of an external RC delay is sufficient for
many of these applications.
The time-out sequence begins from the first rising edge
of MCLR.
Table 5-3 shows the RESET conditions for some spe-
cial registers, while Table 5-4 shows the initialization
conditions for all the registers.
OSC
OSC
(1)
Event
--11 1100
--11 1110
--11 1111
--11 1011
--11 0111
--11 0011
--11 1011
--10 1011
CPUSTA
Wake-up from
1024T
SLEEP
PIC17C7XX
—
(4)
OSC
DS30289B-page 25
OST Active
PP
MCLR Reset
Yes
Yes
Yes
Yes
Yes
Yes
No
No
pin must be
(2)
(2)
(2)
(2)
—
—