PIC17C756A-33/L Microchip Technology Inc., PIC17C756A-33/L Datasheet - Page 156

• Manufacturer Part Number: PIC17C756A-33/L
• Description: 68 PIN, 32 KB OTP, 902 RAM, 50 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC17C756A-33/L

• A/d Inputs: 12-Channel, 10-Bit
• Cpu Speed: 8.25 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/USART
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 32K Bytes
• Ram Size: 902 Bytes
• Speed: 16 MHz
• Timers: 2-8-bit, 2-16-bit
• Voltage, Range: 3-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC17C7XX
15.2.10
A Repeated Start condition occurs when the RSEN bit
(SSPCON2<1>) is programmed high and the I
ule is in the idle state. When the RSEN bit is set, the
SCL pin is asserted low. When the SCL pin is sampled
low, the baud rate generator is loaded with the contents
of SSPADD<6:0> and begins counting. The SDA pin is
released (brought high) for one baud rate generator
count (T
if SDA is sampled high, the SCL pin will be de-asserted
(brought high). When SCL is sampled high the baud
rate generator is reloaded with the contents of
SSPADD<6:0> and begins counting. SDA and SCL
must be sampled high for one T
followed by assertion of the SDA pin (SDA is low) for
one T
bit in the SSPCON2 register will be automatically
cleared and the baud rate generator is not reloaded,
leaving the SDA pin held low. As soon as a START con-
dition is detected on the SDA and SCL pins, the S bit
(SSPSTAT<3>) will be set. The SSPIF bit will not be set
until the baud rate generator has timed out.
FIGURE 15-22:
DS30289B-page 156
Note 1: If the RSEN is programmed while any
BRG
BRG
2: A bus collision during the Repeated Start
while SCL is high. Following this, the RSEN
I
START CONDITION TIMING
). When the baud rate generator times out,
other event is in progress, it will not take
effect.
2
• SDA is sampled low when SCL goes
• SCL goes low before SDA is
condition occurs if:
C MASTER MODE REPEATED
from low to high.
asserted low. This may indicate that
another master is attempting to
transmit a data “1”.
Falling edge of ninth clock
REPEAT START CONDITION WAVEFORM
SDA
SCL
End of Xmit
BRG
. This action is then
Write to SSPCON2
occurs here.
SDA = 1,
SCL (no change)
2
C mod-
T
SDA = 1,
SCL = 1
BRG
T
BRG
Immediately following the SSPIF bit getting set, the
user may write the SSPBUF with the 7-bit address in 7-
bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10-bit mode), or eight bits of data (7-bit
mode).
15.2.10.1
If the user writes the SSPBUF when a Repeated Start
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
Note:
Sr = Repeated Start
T
BRG
At completion of START bit,
hardware clear RSEN bit
Set S (SSPSTAT<3>)
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
and set SSPIF
Write to SSPBUF occurs here
WCOL status flag
T
BRG
1st Bit
T
BRG
2000 Microchip Technology Inc.