PIC18F4550-I/P Microchip Technology Inc., PIC18F4550-I/P Datasheet - Page 78
PIC18F4550-I/P
Manufacturer Part Number
PIC18F4550-I/P
Description
40 PIN, 32 KB FLASH, 2048 RAM, FS-USB 2.0
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F4550-IP.pdf
(430 pages)
Specifications of PIC18F4550-I/P
A/d Inputs
13-Channel, 10-Bit
Comparators
2
Cpu Speed
12 MIPS
Eeprom Memory
256 Bytes
Input Output
34
Interface
I2C/SPI/UART/USART/USB
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
32K Bytes
Ram Size
2K Bytes
Speed
48 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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PIC18F2455/2550/4455/4550
FIGURE 5-8:
DS39632C-page 76
EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)
When a = 0 and f
The instruction executes in
Direct Forced mode. ‘f’ is inter-
preted as a location in the
Access RAM between 060h
and 0FFh. This is the same as
the SFRs or locations F60h to
0FFh (Bank 15) of data
memory.
Locations below 60h are not
available in this addressing
mode.
When a = 0 and f
The instruction executes in
Indexed Literal Offset mode. ‘f’
is interpreted as an offset to the
address value in FSR2. The
two are added together to
obtain the address of the target
register for the instruction. The
address can be anywhere in
the data memory space.
Note that in this mode, the
correct syntax is now:
ADDWF [k], d
where ‘k’ is the same as ‘f’.
When a = 1 (all values of f):
The instruction executes in
Direct mode (also known as
Direct Long mode). ‘f’ is inter-
preted as a location in one of
the 16 banks of the data
memory space. The bank is
designated by the Bank Select
Register (BSR). The address
can be in any implemented
bank in the data memory
space.
COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND
BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)
5Fh:
60h:
Preliminary
FFFh
FFFh
FFFh
F00h
F60h
F00h
F60h
000h
060h
080h
100h
F00h
F60h
000h
080h
100h
000h
080h
100h
Data Memory
Data Memory
Data Memory
Bank 15
Bank 15
Bank 15
Bank 14
Bank 14
Bank 14
Bank 0
through
Bank 0
through
Bank 0
through
Bank 1
Bank 1
Bank 1
SFRs
SFRs
SFRs
00000000
001001da
001001da
BSR
Access RAM
© 2006 Microchip Technology Inc.
FSR2H
ffffffff
ffffffff
FSR2L
FFh
00h
60h
Valid range
for ‘f’
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