PIC18F4550-I/P Microchip Technology Inc., PIC18F4550-I/P Datasheet - Page 180

• Manufacturer Part Number: PIC18F4550-I/P
• Description: 40 PIN, 32 KB FLASH, 2048 RAM, FS-USB 2.0
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4550-I/P

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 34
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2455/2550/4455/4550
17.5.1
The USB Interrupt Status register (Register 17-7) con-
tains the flag bits for each of the USB status interrupt
sources. Each of these sources has a corresponding
interrupt enable bit in the UIE register. All of the USB
status flags are ORed together to generate the USBIF
interrupt flag for the microcontroller’s interrupt funnel.
REGISTER 17-7:
DS39632C-page 178
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
U-0
—
2:
3:
4:
Once an Idle state is detected, the user may want to place the USB module in Suspend mode.
Clearing this bit will cause the USTAT FIFO to advance (valid only for IN, OUT and SETUP tokens).
This bit is typically unmasked only following the detection of a UIDLE interrupt event.
Only error conditions enabled through the UEIE register will set this bit. This bit is a status bit only and
cannot be set or cleared by the user.
USB INTERRUPT STATUS
REGISTER (UIR)
Unimplemented: Read as ‘0’
SOFIF: START-OF-FRAME Token Interrupt bit
1 = A START-OF-FRAME token received by the SIE
0 = No START-OF-FRAME token received by the SIE
STALLIF: A STALL Handshake Interrupt bit
1 = A STALL handshake was sent by the SIE
0 = A STALL handshake has not been sent
IDLEIF: Idle Detect Interrupt bit
1 = Idle condition detected (constant Idle state of 3 ms or more)
0 = No Idle condition detected
TRNIF: Transaction Complete Interrupt bit
1 = Processing of pending transaction is complete; read USTAT register for endpoint information
0 = Processing of pending transaction is not complete or no transaction is pending
ACTVIF: Bus Activity Detect Interrupt bit
1 = Activity on the D+/D- lines was detected
0 = No activity detected on the D+/D- lines
UERRIF: USB Error Condition Interrupt bit
1 = An unmasked error condition has occurred
0 = No unmasked error condition has occurred.
URSTIF: USB Reset Interrupt bit
1 = Valid USB Reset occurred; 00h is loaded into UADDR register
0 = No USB Reset has occurred
SOFIF
R/W-0
UIR: USB INTERRUPT STATUS REGISTER
W = Writable bit
‘1’ = Bit is set
STALLIF
R/W-0
IDLEIF
(1)
R/W-0
Preliminary
(1)
(3)
(2)
(4)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TRNIF
R/W-0
Once an interrupt bit has been set by the SIE, it must
be cleared by software by writing a ‘0’. The flag bits
can also be set in software which can aid in firmware
debugging.
(2)
ACTVIF
R/W-0
(3)
© 2006 Microchip Technology Inc.
x = Bit is unknown
UERRIF
R-0
(4)
URSTIF
R/W-0
bit 0