PIC18F4550-I/P Microchip Technology Inc., PIC18F4550-I/P Datasheet - Page 308

• Manufacturer Part Number: PIC18F4550-I/P
• Description: 40 PIN, 32 KB FLASH, 2048 RAM, FS-USB 2.0
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4550-I/P

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 34
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2455/2550/4455/4550
Even when the dedicated port is enabled, the ICSP and
ICD functions remain available through the legacy port.
When V
of the ICRST/ICV
25.9.2
PIC18F4455/4550 devices in 44-pin TQFP packages
also have the ability to change their configuration under
external control for debugging purposes. This allows
the device to behave as if it were a PIC18F2455/2550
28-pin device.
This 28-pin Configuration mode is controlled through a
single pin, NC/ICPORTS. Connecting this pin to V
forces the device to function as a 28-pin device.
Features normally associated with the 40/44-pin
devices are disabled along with their corresponding
control registers and bits. This includes PORTD and
PORTE, the SPP and the Enhanced PWM functionality
of CCP1. On the other hand, connecting the pin to V
forces the device to function in its default configuration.
The configuration option is only available when back-
ground debugging and the dedicated ICD/ICSP port
are both enabled (DEBUG Configuration bit is clear
and ICPRT Configuration bit is set). When disabled,
NC/ICPORTS is a No Connect pin.
25.10 Single-Supply ICSP Programming
The LVP Configuration bit enables Single-Supply ICSP
Programming (formerly known as Low-Voltage ICSP
Programming or LVP) . When Single-Supply Program-
ming
programmed without requiring high voltage being
applied
RB5/KBI1/PGM pin is then dedicated to controlling
Program mode entry and is not available as a general
purpose I/O pin.
While programming using Single-Supply Program-
ming, V
normal execution mode. To enter Programming mode,
V
DS39632C-page 306
DD
Note 1: The ICPRT Configuration bit can only be
is applied to the PGM pin.
is
IH
DD
2: The ICPRT Configuration bit must be
to
is seen on the MCLR/V
is applied to the MCLR/V
enabled,
28-PIN EMULATION
programmed through the default ICSP
port.
maintained clear for all 28-pin and 40-pin
devices; otherwise, unexpected operation
may occur.
the
PP
pin is ignored.
MCLR/V
the
microcontroller
PP
/RE3
PP
/RE3 pin, the state
PP
pin,
/RE3 pin as in
but
can
Preliminary
the
DD
be
SS
If Single-Supply ICSP Programming mode will not be
used, the LVP bit can be cleared. RB5/KBI1/PGM then
becomes available as the digital I/O pin, RB5. The LVP
bit may be set or cleared only when using standard
high-voltage programming (V
MCLR/V
only the standard high-voltage programming is
available and must be used to program the device.
Memory that is not code-protected can be erased using
either a Block Erase, or erased row by row, then written
at any specified V
erased, a Block Erase is required. If a Block Erase is to
be performed when using Low-Voltage Programming,
the device must be supplied with V
Note 1: High-Voltage Programming is always
PP
2: While in Low-Voltage ICSP Programming
3: When using Low-Voltage ICSP Program-
4: If the device Master Clear is disabled,
/RE3 pin). Once LVP has been disabled,
available, regardless of the state of the
LVP bit, by applying V
mode, the RB5 pin can no longer be used
as a general purpose I/O pin and should
be held low during normal operation.
ming (LVP) and the pull-ups on PORTB
are enabled, bit 5 in the TRISB register
must be cleared to disable the pull-up on
RB5 and ensure the proper operation of
the device.
verify that either of the following is done to
ensure proper entry into ICSP mode:
a) disable Low-Voltage Programming
b) make certain that RB5/KBI1/PGM
(CONFIG4L<2> = 0); or
is held low during entry into ICSP.
DD
. If code-protected memory is to be
© 2006 Microchip Technology Inc.
IHH
IHH
DD
to the MCLR pin.
applied to the
of 4.5V to 5.5V.