PIC18F4550-I/P Microchip Technology Inc., PIC18F4550-I/P Datasheet - Page 47

• Manufacturer Part Number: PIC18F4550-I/P
• Description: 40 PIN, 32 KB FLASH, 2048 RAM, FS-USB 2.0
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4550-I/P

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 34
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

4.2
The MCLR pin provides a method for triggering an
external Reset of the device. A Reset is generated by
holding the pin low. These devices have a noise filter in
the MCLR Reset path which detects and ignores small
pulses.
The MCLR pin is not driven low by any internal Resets,
including the WDT.
In PIC18F2455/2550/4455/4550 devices, the MCLR
input can be disabled with the MCLRE Configuration
bit. When MCLR is disabled, the pin becomes a digital
input. See Section 10.5 “PORTE, TRISE and LATE
Registers” for more information.
4.3
A Power-on Reset pulse is generated on-chip
whenever V
allows the device to start in the initialized state when
V
To take advantage of the POR circuitry, tie the MCLR pin
through a resistor (1 k
eliminate external RC components usually needed to
create a Power-on Reset delay. A minimum rise rate for
V
Characteristics”). For a slow rise time, see Figure 4-2.
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
POR events are captured by the POR bit (RCON<1>).
The state of the bit is set to ‘0’ whenever a POR occurs;
it does not change for any other Reset event. POR is
not reset to ‘1’ by any hardware event. To capture
multiple events, the user manually resets the bit to ‘1’
in software following any POR.
© 2006 Microchip Technology Inc.
DD
DD
is adequate for operation.
is specified (parameter D004, Section 28.1 “DC
Master Clear Reset (MCLR)
Power-on Reset (POR)
DD
rises above a certain threshold. This
to 10 k ) to V
DD
. This will
PIC18F2455/2550/4455/4550
Preliminary
FIGURE 4-2:
Note 1: External Power-on Reset circuit is required
V
DD
2: R < 40 k is recommended to make sure that
3: R1
D
only if the V
The diode D helps discharge the capacitor
quickly when V
the voltage drop across R does not violate
the device’s electrical specification.
MCLR from external capacitor C, in the event
of MCLR/V
static
Overstress (EOS).
V
DD
R
1 k
C
Discharge
PP
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW V
will limit any current flowing into
DD
pin breakdown, due to Electro-
R1
DD
power-up slope is too slow.
powers down.
(ESD)
DD
PIC18FXXXX
MCLR
POWER-UP)
DS39632C-page 45
or
Electrical