PIC18F4550-I/P Microchip Technology Inc., PIC18F4550-I/P Datasheet - Page 171

• Manufacturer Part Number: PIC18F4550-I/P
• Description: 40 PIN, 32 KB FLASH, 2048 RAM, FS-USB 2.0
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4550-I/P

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 34
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

17.2.4
Each of the 16 possible bidirectional endpoints has its
own independent control register, UEPn (where ‘n’ rep-
resents the endpoint number). Each register has an
identical complement of control bits. The prototype is
shown in Register 17-4.
The EPHSHK bit (UEPn<4>) controls handshaking for
the endpoint; setting this bit enables USB handshaking.
Typically, this bit is always set except when using
isochronous endpoints.
The EPCONDIS bit (UEPn<3>) is used to enable or
disable USB control operations (SETUP) through the
endpoint. Clearing this bit enables SETUP transac-
tions. Note that the corresponding EPINEN and
EPOUTEN bits must be set to enable IN and OUT
REGISTER 17-4:
© 2006 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
U-0
—
Valid only if Endpoint n is enabled; otherwise, the bit is ignored.
USB ENDPOINT CONTROL
Unimplemented: Read as ‘0’
EPHSHK: Endpoint Handshake Enable bit
1 = Endpoint handshake enabled
0 = Endpoint handshake disabled (typically used for isochronous endpoints)
EPCONDIS: Bidirectional Endpoint Control bit
If EPOUTEN = 1 and EPINEN = 1:
1 = Disable Endpoint n from control transfers; only IN and OUT transfers allowed
0 = Enable Endpoint n for control (SETUP) transfers; IN and OUT transfers also allowed
EPOUTEN: Endpoint Output Enable bit
1 = Endpoint n output enabled
0 = Endpoint n output disabled
EPINEN: Endpoint Input Enable bit
1 = Endpoint n input enabled
0 = Endpoint n input disabled
EPSTALL: Endpoint Stall Enable bit
1 = Endpoint n is stalled
0 = Endpoint n is not stalled
U-0
—
UEPn: USB ENDPOINT n CONTROL REGISTER (UEP0 THROUGH UEP15)
W = Writable bit
‘1’ = Bit is set
U-0
—
PIC18F2455/2550/4455/4550
EPHSHK
R/W-0
Preliminary
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
EPCONDIS
R/W-0
transactions. For Endpoint 0, this bit should always be
cleared
Endpoint 0 as the default control endpoint.
The EPOUTEN bit (UEPn<2>) is used to enable or dis-
able USB OUT transactions from the host. Setting this
bit enables OUT transactions. Similarly, the EPINEN bit
(UEPn<1>) enables or disables USB IN transactions
from the host.
The EPSTALL bit (UEPn<0>) is used to indicate a
STALL condition for the endpoint. If a STALL is issued
on a particular endpoint, the EPSTALL bit for that end-
point pair will be set by the SIE. This bit remains set
until it is cleared through firmware, or until the SIE is
reset.
since
EPOUTEN
R/W-0
the
USB
x = Bit is unknown
EPINEN
R/W-0
specifications
DS39632C-page 169
EPSTALL
R/W-0
identify
bit 0
(1)