PIC18F4550-I/P Microchip Technology Inc., PIC18F4550-I/P Datasheet - Page 164
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
PIC18F4550-I/P
Manufacturer Part Number
PIC18F4550-I/P
Description
40 PIN, 32 KB FLASH, 2048 RAM, FS-USB 2.0
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F4550-IP.pdf
(430 pages)
Specifications of PIC18F4550-I/P
A/d Inputs
13-Channel, 10-Bit
Comparators
2
Cpu Speed
12 MIPS
Eeprom Memory
256 Bytes
Input Output
34
Interface
I2C/SPI/UART/USART/USB
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
32K Bytes
Ram Size
2K Bytes
Speed
48 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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PIC18F2455/2550/4455/4550
TABLE 16-3:
DS39632C-page 162
INTCON
RCON
IPR1
PIR1
PIE1
IPR2
PIR2
PIE2
TRISB
TRISC
TRISD
TMR1L
TMR1H
T1CON
TMR2
T2CON
PR2
TMR3L
TMR3H
T3CON
CCPR1L
CCPR1H
CCP1CON
ECCP1AS
ECCP1DEL
Legend:
Note 1:
Name
(2)
2:
— = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.
The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
These bits or registers are unimplemented in 28-pin devices; always maintain these bits clear.
Timer1 Register Low Byte
Timer1 Register High Byte
Timer2 Module Register
Timer2 Period Register
Timer3 Register Low Byte
Timer3 Register High Byte
Capture/Compare/PWM Register 1 (LSB)
Capture/Compare/PWM Register 1 (MSB)
ECCPASE
GIE/GIEH
SPPIP
SPPIF
SPPIE
OSCFIP
OSCFIF
OSCFIE
TRISB7
TRISC7
TRISD7
P1M1
PRSEN
RD16
RD16
IPEN
Bit 7
—
REGISTERS ASSOCIATED WITH ECCP MODULE AND TIMER1 TO TIMER3
(2)
(2)
(2)
(2)
SBOREN
T2OUTPS3 T2OUTPS2 T2OUTPS1
PEIE/GIEL
ECCPAS2
T3CCP2
PDC6
TRISB6
TRISC6
TRISD6
P1M0
T1RUN
CMIP
CMIF
CMIE
ADIP
ADIF
ADIE
Bit 6
(2)
(2)
(1)
ECCPAS1
T1CKPS1
T3CKPS1
TMR0IE
PDC5
TRISB5
TRISD5
DC1B1
USBIP
USBIF
USBIE
RCIP
RCIF
RCIE
Bit 5
—
—
(2)
ECCPAS0
T1CKPS0
T3CKPS0
PDC4
TRISB4
TRISD4
Preliminary
DC1B0
INT0IE
TXIP
TXIE
EEIP
EEIF
EEIE
Bit 4
TXIF
RI
—
(2)
T2OUTPS0
T1OSCEN
T3CCP1
CCP1M3
PSSAC1
TRISB3
TRISD3
PDC3
SSPIP
SSPIF
SSPIE
BCLIP
BCLIE
BCLIF
RBIE
Bit 3
TO
—
(2)
TMR2ON
T1SYNC
T3SYNC
CCP1M2
PSSAC0
TMR0IF
CCP1IP
CCP1IF
CCP1IE
HLVDIP
HLVDIE
TRISB2
TRISC2
TRISD2
PDC2
HLVDIF
Bit 2
PD
(2)
PSSBD1
T2CKPS1
TMR1CS
TMR3CS
CCP1M1
TMR2IP
TMR2IF
TMR2IE
TMR3IP
TMR3IF
TMR3IE
TRISC1
TRISD1
© 2006 Microchip Technology Inc.
TRISB1
PDC1
INT0IF
Bit 1
POR
(2)
(2)
PSSBD0
TMR1ON
T2CKPS0
TMR3ON
CCP1M0
TMR1IP
TMR1IF
TMR1IE
CCP2IP
CCP2IF
CCP2IE
TRISB0
TRISC0
TRISD0
PDC0
RBIF
Bit 0
BOR
(2)
(2)
on page
Values
Reset
51
52
54
54
54
54
54
54
54
54
52
52
52
52
52
52
53
53
53
53
53
53
53
53
54
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