CY7C68001-56PVXC Cypress Semiconductor Corp, CY7C68001-56PVXC Datasheet - Page 4

• Manufacturer Part Number: CY7C68001-56PVXC
• Description: IC USB INTERFACE SX2 56-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: USBr
• Series: CY7Cr

Specifications of CY7C68001-56PVXC

• Package / Case: 56-SSOP
• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: 0 C to + 70 C
• Operating Supply Voltage: 3.3 V
• Core Size: 8 Bit
• No. Of I/o's: 35
• Ram Memory Size: 256Byte
• Embedded Interface Type: SPI, USB
• Digital Ic Case Style: SSOP
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1864; CY7C68001-56PVXC

Bit 6: EP0BUF
If this interrupt is enabled, and the Endpoint 0 buffer becomes
available to the external master for read or write operations, the
SX2 asserts the INT# pin and sets bit 6 in the Interrupt Status
Byte. This interrupt is used for handling the data phase of a setup
request. For complete details on how to handle the EP0BUF
interrupt, refer to
Bit 5: FLAGS
If this interrupt is enabled, and any OUT endpoint FIFO’s state
changes from empty to not empty and from not empty to empty,
the SX2 asserts the INT# pin and sets bit 5 in the Interrupt Status
Byte. This is an alternate way to monitor the status of OUT
endpoint FIFOs instead of using the FLAGA-FLAGD pins, and
can be used to indicate when an OUT packet has been received
from the host.
Bit 2: ENUMOK
If this interrupt is enabled and the SX2 receives a
SET_CONFIGURATION request from the USB host, the SX2
asserts the INT# pin and sets bit 2 in the Interrupt Status Byte.
This event signals the completion of the SX2 enumeration
process.
Bit 1: BUSACTIVITY
If this interrupt is enabled, and the SX2 detects either an absence
or resumption of activity on the USB bus, the SX2 asserts the
INT# pin and sets bit 1 in the Interrupt Status Byte. This usually
indicates that the USB host is either suspending or resuming or
that a self-powered device has been plugged in or unplugged. If
the SX2 is bus-powered, the external master must put the SX2
into a low power mode after detecting a USB suspend condition
to be USB-compliant.
Bit 0: READY
If this interrupt is enabled, bit 0 in the Interrupt Status Byte is set
when the SX2 has powered up and performed a self-test. The
external master should always wait for this interrupt before trying
to read or write to the SX2, unless an external EEPROM with a
valid descriptor is present. If an external EEPROM with a valid
descriptor is present, the ENUMOK interrupt occurs instead of
the READY interrupt after power up. A READY interrupt also
occurs if the SX2 is awakened from a low power mode via the
WAKEUP pin. This READY interrupt indicates that the SX2 is
ready for commands or data.
5.4.3 Qualify with READY Pin on Register Reads
It is true that all interrupts are buffered after a command read
request has been initiated. However, in very rare conditions,
there might be a situation when there is a pending interrupt
already, when a read request is initiated by the external master.
In this case it is the interrupt status byte that is output when the
external master asserts the SLRD. So, a condition exists where
the Interrupt Status Data Byte can be mistaken for the result of a
command register read request. In order to get around this
possible race condition, the first thing that the external master
must do on getting an interrupt from the SX2 is check the status
Document #: 38-08013 Rev. *J
Note
3. If the descriptor loaded is set for remote wakeup enabled and the host does a set feature remote wakeup enabled, then the SX2 logic performs RESUME signalling
after a WAKEUP interrupt.
Endpoint 0
on page 8 of this data sheet.
of the READY pin. If the READY is low at the time the INT# was
asserted, the data that is output when the external master
strobes the SLRD is the interrupt status byte (not the actual data
requested). If the READY pin is high at the time when the
interrupt is asserted, the data output on strobing the SLRD is the
actual data byte requested by the external master. So it is
important that the state of the READY pin be checked at the time
the INT# is asserted to ascertain the cause of the interrupt.
5.5 Resets and Wakeup
5.5.1 Reset
An input pin (RESET#) resets the chip. The internal PLL stabi-
lizes after V
network (R = 100 KOhms, C = 0.1 μF) is used to provide the
RESET# signal. The Clock must be in a stable state for at least
200 μs before the RESET is released.
5.5.2 USB Reset
When the SX2 detects a USB Reset condition on the USB bus,
SX2 handles it like any other enumeration sequence. This
means that SX2 enumerates again and assert the ENUMOK
interrupt to let the external master know that it has enumerated.
The external master is then responsible for configuring the SX2
for the application. The external master should also check
whether SX2 enumerated at High or Full speed in order to adjust
the EPxPKTLENH/L register values accordingly. The last initial-
ization task is for the external master to flush all of the SX2
FIFOs.
5.5.3 Wakeup
The SX2 exits its low power state when one of the following
events occur:
■
■
5.6 Endpoint RAM
5.6.1 Size
■
■
Organization
■
■
USB bus signals a resume. The SX2 asserts a BUSACTIVITY
interrupt.
The external master asserts the WAKEUP pin. The SX2 asserts
a READY interrupt
Control endpoint: 64 Bytes: 1 × 64 bytes (Endpoint 0).
FIFO Endpoints: 4096 Bytes: 8 × 512 bytes (Endpoint 2, 4, 6, 8).
EP0–Bidirectional Endpoint 0, 64-byte buffer.
EP2, 4, 6, 8–Eight 512-byte buffers, bulk, interrupt, or isoch-
ronous. EP2 and EP6 can be either double-, triple-, or
quad-buffered. EP4 and EP8 can only be double-buffered. For
high speed endpoint configuration options, see
page 11.
CC
has reached 3.3V. Typically, an external RC
[3]
.
CY7C68001
Figure 8-1.
Page 4 of 45
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