CY7C68001-56PVXC Cypress Semiconductor Corp, CY7C68001-56PVXC Datasheet - Page 33

• Manufacturer Part Number: CY7C68001-56PVXC
• Description: IC USB INTERFACE SX2 56-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: USBr
• Series: CY7Cr

Specifications of CY7C68001-56PVXC

• Package / Case: 56-SSOP
• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: 0 C to + 70 C
• Operating Supply Voltage: 3.3 V
• Core Size: 8 Bit
• No. Of I/o's: 35
• Ram Memory Size: 256Byte
• Embedded Interface Type: SPI, USB
• Digital Ic Case Style: SSOP
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1864; CY7C68001-56PVXC

13.1 Slave FIFO Output Enable
Following timings are applicable to synchronous and asynchronous interfaces.
Table 13-19. Slave FIFO Output Enable Parameters
13.1 Sequence Diagram
Document #: 38-08013 Rev. *J
t
t
OEon
OEoff
FIFOADR
FLAGS
FIFO POINTER
DATA
FIFO DATA BUS
IFCLK
SLRD
SLCS
SLOE
Parameter
Not Driven
t=0
IFCLK
N
SLOE assert to FIFO DATA Output
SLOE deassert to FIFO DATA Hold
Figure 13-16. Slave FIFO Synchronous Read Sequence and Timing Diagram
t=1
SLOE
t
SFA
Figure 13-17. Slave FIFO Synchronous Sequence of Events Diagram
t
OEon
Data Driven: N
t=2
Driven: N
Figure 13-15. Slave FIFO Output Enable Timing Diagram
t
DATA
SRD
SLOE
IFCLK
N
t
IFCLK
t
XFD
t=3
t
RDH
SLRD
t
XFLG
Description
t
OEoff
N+1
t=4
t
N+1
FAH
IFCLK
N+1
SLOE
SLRD
Not Driven
IFCLK
t
T=0
N+1
SFA
t
OEon
t
OEon
SLOE
T=2
>= t
T=1
N+1
IFCLK
N+1
SRD
N+1
SLRD
t
t
OEoff
XFD
Min
N+2
N+2
IFCLK
N+2
N+3
N+3
IFCLK
t
XFD
[12]
N+4
N+4
Max
10.5
10.5
IFCLK
N+3
SLRD
t
>= t
XFD
RDH
N+4
N+4
IFCLK
t
N+4
OEoff
CY7C68001
SLOE
T=3
T=4
t
FAH
Unit
ns
ns
Page 33 of 45
Not Driven
IFCLK
N+4
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