CY7C68001-56PVXC Cypress Semiconductor Corp, CY7C68001-56PVXC Datasheet - Page 28

IC USB INTERFACE SX2 56-SSOP

CY7C68001-56PVXC

Manufacturer Part Number
CY7C68001-56PVXC
Description
IC USB INTERFACE SX2 56-SSOP
Manufacturer
Cypress Semiconductor Corp
Type
USBr
Series
CY7Cr
Datasheet

Specifications of CY7C68001-56PVXC

Package / Case
56-SSOP
Protocol
USB 2.0
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Temperature Range
0 C to + 70 C
Operating Supply Voltage
3.3 V
Core Size
8 Bit
No. Of I/o's
35
Ram Memory Size
256Byte
Embedded Interface Type
SPI, USB
Digital Ic Case Style
SSOP
Supply Voltage Range
3V To 3.6V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
428-1864
CY7C68001-56PVXC

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C68001-56PVXC
Manufacturer:
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Quantity:
101
Part Number:
CY7C68001-56PVXC
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Quantity:
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Part Number:
CY7C68001-56PVXC
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Part Number:
CY7C68001-56PVXC
0
Table 13-7. Slave FIFO Synchronous Read with Internally Sourced IFCLK
Table 13-9. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK
Document #: 38-08013 Rev. *J
t
t
t
t
t
t
t
t
t
t
t
t
t
Table 13-8. Slave FIFO Synchronous Read with Externally Sourced IFCLK
IFCLK
SRD
RDH
OEon
OEoff
XFLG
XFD
t
t
t
t
t
t
t
IFCLK
SWR
WRH
SFD
FDH
XFLG
IFCLK
SRD
RDH
OEon
OEoff
XFLG
XFD
Parameter
Parameter
Parameter
IFCLK Period
SLWR to Clock Setup Time
Clock to SLWR Hold Time
FIFO Data to Clock Setup Time
Clock to FIFO Data Hold Time
Clock to FLAGS Output Propagation Time
IFCLK Period
SLRD to Clock Setup Time
Clock to SLRD Hold Time
SLOE Turn on to FIFO Data Valid
SLOE Turn off to FIFO Data Hold
Clock to FLAGS Output Propagation Delay
Clock to FIFO Data Output Propagation Delay
IFCLK Period
SLRD to Clock Setup Time
Clock to SLRD Hold Time
SLOE Turn on to FIFO Data Valid
SLOE Turn off to FIFO Data Hold
Clock to FLAGS Output Propagation Delay
Clock to FIFO Data Output Propagation Delay
FLAGS
IFCLK
SLWR
DATA
Figure 13-6. Slave FIFO Synchronous Write Timing Diagram
Description
Description
Description
t
SWR
t
SFD
t
IFCLK
t
WRH
t
N
t
XFLG
FDH
[14]
[14]
20.83
18.1
Min
9.2
0
0
20.83
12.7
18.7
Min
Min
3.7
20
0
[14]
[13]
Max
9.5
Max
10.5
10.5
13.5
Max
10.5
10.5
200
9.5
15
11
CY7C68001
Unit
ns
ns
ns
ns
ns
ns
Page 28 of 45
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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