CY7C68001-56PVXC Cypress Semiconductor Corp, CY7C68001-56PVXC Datasheet - Page 18

• Manufacturer Part Number: CY7C68001-56PVXC
• Description: IC USB INTERFACE SX2 56-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: USBr
• Series: CY7Cr

Specifications of CY7C68001-56PVXC

• Package / Case: 56-SSOP
• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: 0 C to + 70 C
• Operating Supply Voltage: 3.3 V
• Core Size: 8 Bit
• No. Of I/o's: 35
• Ram Memory Size: 256Byte
• Embedded Interface Type: SPI, USB
• Digital Ic Case Style: SSOP
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1864; CY7C68001-56PVXC

These flags can be programmed to represent various FIFO flags
using four select bits for each FIFO. The 4-bit coding for all four
flags is the same, as shown in
.
Table 9-2. FIFO Flag 4-bit Coding
For the default (0000) selection, the four FIFO flags are
fixed-function as shown in the first table entry; the input pins
FIFOADR[2:0] select to which of the four FIFOs the flags corre-
spond. These pins are decoded as shown in
The other (non-zero) values of FLAGx[3:0] allow the designer to
independently configure the four flag outputs FLAGA-FLAGD to
correspond to any flag-Programmable, Full, or Empty-from any
of the four endpoint FIFOs. This allows each flag to be assigned
to any of the four FIFOs, including those not currently selected
by the FIFOADR [2:0] pins. For example, the external master
could be filling the EP2IN FIFO with data while also checking the
empty flag for the EP4OUT FIFO.
9.3 POLAR Register 0x04
This register controls the polarities of FIFO pin signals and the
WAKEUP pin.
Document #: 38-08013 Rev. *J
FLAGx3 FLAGx2 FLAGx1 FLAGx0
POLAR
Bit #
Bit
Name
Read/
Write
Default
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
WUPOL
R/W
7
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
R/W
6
0
0
PKTEND SLOE
R/W
5
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Table
R
4
0
9-2.
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
SLRD SLWR
R
3
0
FLAGA = PF,
FLAGB = FF,
FLAGC = EF,
FLAGD = CS#
(actual FIFO is
selected by
FIFOADR[2:0]
pins)
Reserved
Reserved
Reserved
EP2 PF
EP4 PF
EP6 PF
EP8 PF
EP2 EF
EP4 EF
EP6 EF
EP8 EF
EP2 FF
EP4 FF
EP6 FF
EP8 FF
Table
Pin Function
R
2
0
5-3.
R/W
EF
1
0
R/W
0x04
FF
0
0
9.3.1 Bit 7: WUPOL
This flag sets the polarity of the WAKEUP pin. If WUPOL = 0
(default), the polarity is active LOW. If WUPOL=1, the polarity is
active HIGH.
9.3.2 Bit 5: PKTEND
This flag selects the polarity of the PKTEND pin. If PKTEND = 0
(default), the polarity is active LOW. If PKTEND = 1, the polarity
is active HIGH.
9.3.3 Bit 4: SLOE
This flag selects the polarity of the SLOE pin. If SLOE = 0
(default), the polarity is active LOW. If SLOE = 1, the polarity is
active HIGH. This bit can only be changed by using the EEPROM
configuration load.
9.3.4 Bit 3: SLRD
This flag selects the polarity of the SLRD pin. If SLRD = 0
(default), the polarity is active LOW. If SLRD = 1, the polarity is
active HIGH. This bit can only be changed by using the EEPROM
configuration load.
9.3.5 SLWR Bit 2
This flag selects the polarity of the SLWR pin. If SLWR = 0
(default), the polarity is active LOW. If SLWR = 1, the polarity is
active HIGH. This bit can only be changed by using the EEPROM
configuration load.
9.3.6 EF Bit 1
This flag selects the polarity of the EF pin (FLAGA/B/C/D). If EF
= 0 (default), the EF pin is pulled low when the FIFO is empty. If
EF = 1, the EF pin is pulled HIGH when the FIFO is empty.
9.3.7 FF Bit 0
This flag selects the polarity of the FF pin (FLAGA/B/C/D). If FF
= 0 (default), the FF pin is pulled low when the FIFO is full. If
FF = 1, the FF pin is pulled HIGH when the FIFO is full.
Note that bits 2(SLWR), 3(SLRD) and 4 (SLOE) are READ only
bits and cannot be set by the external master or the EEPROM.
On power up, these bits are set to active low polarity. In order to
change the polarity after the device is powered-up, the external
master must access the previously undocumented (un-indexed)
SX2 register located at XDATA space at 0xE609. This register
has exact same bit definition as the POLAR register except that
bits 2, 3 and 4 defined as SLWR, SLRD and SLOE respectively
are Read/Write bits. Following is the sequence of events that the
master should perform for setting this register to 0x1C (setting
bits 4, 3, and 2):
1. Send Low Byte of the Register (0x09)
2. Send High Byte of the Register (0xE6)
a. Command address write of address 0x3A
b. Command data write of upper nibble of the Low Byte of
c. Command data write of lower nibble of the Low Byte of
d. Command address write of address 0x3B
e. Command data write of upper nibble of the High Byte of
f. Command data write of lower nibble of the High Byte of
Register Address (0x00)
Register Address (0x09)
Register Address (0x0E)
Register Address (0x06)
CY7C68001
Page 18 of 45
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