LAN9311-NU SMSC, LAN9311-NU Datasheet - Page 56

• Manufacturer Part Number: LAN9311-NU
• Description: IC ETHER SW 2PRT 16BIT 128-VTQFP
• Manufacturer: SMSC
• Type: Two Port Managed Ethernet Switchr

Specifications of LAN9311-NU

• Controller Type: Ethernet Switch Controller
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Product: Ethernet Switches
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Maximum Operating Temperature: + 70 C
• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• For Use With: 638-1076 - EVALUATION BOARD LAN9311-NU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1075

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
6.2.1
Switch Fabric CSR Writes
To perform a write to an individual switch fabric register, the desired data must first be written into the
Switch Fabric CSR Interface Data Register
(SWITCH_CSR_DATA). The write cycle is initiated by
p e r f o r m i n g a s i n g l e w r i t e t o t h e
S w i t c h F a b r i c C S R I n t e r f a c e C o m m a n d R e g i s t e r
(SWITCH_CSR_CMD)
with CSR_BUSY (bit 31) set, the CSR_ADDRESS field (bits 15:0) set to the
desired register address, the R_nW (bit 30) cleared, the AUTO_INC and AUTO_DEC fields cleared,
and the desired CSR byte enable bits selected (bits 19:16). The completion of the write cycle is
indicated by the clearing of the CSR_BUSY bit.
A second write method may be used which utilizes the auto increment/decrement function of the
Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD)
for writing sequential register
addresses. When using this method, the
Switch Fabric CSR Interface Command Register
(SWITCH_CSR_CMD)
must first be written with the auto increment(AUTO_INC) or auto
decrement(AUTO_DEC) bit set, the CSR_ADDRESS field written with the desired register address, the
R_nW bit cleared, and the desired CSR byte enable bits selected (typically all set). The write cycles
are then initiated by writing the desired data into the
Switch Fabric CSR Interface Data Register
(SWITCH_CSR_DATA). The completion of the write cycle is indicated by the clearing of the
CSR_BUSY bit, at which time the address in the
Switch Fabric CSR Interface Command Register
(SWITCH_CSR_CMD)
is incremented or decremented accordingly. The user may then initiate a
subsequent write cycle by writing the desired data into the
Switch Fabric CSR Interface Data Register
(SWITCH_CSR_DATA).
The third write method is to use the direct data range write function. Writes within the
Switch Fabric
CSR Interface Direct Data Register (SWITCH_CSR_DIRECT_DATA)
address range automatically set
the appropriate register address, set all four byte enable bits (CSR_BE[3:0]), clears the R_nW bit, and
s e t s t h e C S R _ B U S Y b i t o f t h e
S w i t c h F a b r i c C S R I n t e r f a c e C o m m a n d R e g i s t e r
(SWITCH_CSR_CMD). The completion of the write cycle is indicated by the clearing of the
CSR_BUSY bit. Since the address range of the switch fabric CSRs exceeds that of the
Switch Fabric
CSR Interface Direct Data Register (SWITCH_CSR_DIRECT_DATA)
address range, a sub-set of the
switch fabric CSRs are mapped to the
Switch Fabric CSR Interface Direct Data Register
(SWITCH_CSR_DIRECT_DATA)
address range as detailed in
Table 14.3, “Switch Fabric CSR to
SWITCH_CSR_DIRECT_DATA Address Range Map,” on page
241.
Figure 6.1
illustrates the process required to perform a switch fabric CSR write. The minimum wait
periods as specified in
Table 8.1, “Read After Write Timing Rules,” on page 103
are required where
noted.
Revision 1.7 (06-29-10)
56
SMSC LAN9311/LAN9311i
DATASHEET