LAN9311-NU SMSC, LAN9311-NU Datasheet
LAN9311-NU
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LAN9311-NU Summary of contents
Page 1
... Programmable filter by MAC address Switch Management — Port mirroring/monitoring/sniffing: ingress and/or egress traffic on any ports or port pairs — Fully compliant statistics (MIB) gathering counters — Control registers configurable on-the-fly SMSC LAN9311/LAN9311i LAN9311/LAN9311i Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Ports — ...
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... LAN9311-NU For 128-Pin, VTQFP Lead-Free RoHS Compliant Package (0 TO 70°C Temp Range) LAN9311-NZW For 128-Pin, XVTQFP Lead-Free RoHS Compliant Package (0 TO 70°C Temp Range) LAN9311i-NZW For 128-Pin, XVTQFP Lead-Free RoHS Compliant Package (-40 TO 85°C Temp Range) This product meets the halogen maximum concentration values per IEC61249-2-21 ...
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... Host MAC Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Chapter 5 System Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.2 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.2.1 1588 Time Stamp Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.2.2 Switch Fabric Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.2.3 Ethernet PHY Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.2.4 GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.2.5 Host MAC Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.2.6 Power Management Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 SMSC LAN9311/LAN9311i 3 DATASHEET Revision 1.7 (06-29-10) ...
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... Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7.2.1.1 MII MAC Interface ........................................................................................................................................................................................... 84 7.2.1.2 4B/5B Encoder................................................................................................................................................................................................ 84 7.2.1.3 Scrambler and PISO ....................................................................................................................................................................................... 86 7.2.1.4 NRZI and MLT-3 Encoding ............................................................................................................................................................................. 86 7.2.1.5 100M Transmit Driver ..................................................................................................................................................................................... 86 Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 4 DATASHEET Datasheet SMSC LAN9311/LAN9311i ...
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... PIO Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 8.5.5 PIO Burst Reads 108 8.5.6 RX Data FIFO Direct PIO Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 8.5.7 RX Data FIFO Direct PIO Burst Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.5.8 PIO Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8.5.9 TX Data FIFO Direct PIO Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 SMSC LAN9311/LAN9311i 5 DATASHEET Revision 1.7 (06-29-10) ...
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... ERASE (Erase Location) .............................................................................................................................................................................. 146 10.2.3.3 ERAL (Erase All)........................................................................................................................................................................................... 147 10.2.3.4 EWDS (Erase/Write Disable) ........................................................................................................................................................................ 147 10.2.3.5 EWEN (Erase/Write Enable)......................................................................................................................................................................... 148 10.2.3.6 READ (Read Location) ................................................................................................................................................................................. 148 Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 6 DATASHEET Datasheet SMSC LAN9311/LAN9311i ...
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... Host MAC RX Dropped Frames Counter Register (RX_DROP)................................................................................................................... 187 14.2.2.7 Host MAC CSR Interface Command Register (MAC_CSR_CMD)............................................................................................................... 188 14.2.2.8 Host MAC CSR Interface Data Register (MAC_CSR_DATA) ...................................................................................................................... 189 14.2.2.9 Host MAC Automatic Flow Control Configuration Register (AFC_CFG) ...................................................................................................... 190 SMSC LAN9311/LAN9311i 7 DATASHEET Revision 1.7 (06-29-10) ...
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... Host MAC MII Data Register (HMAC_MII_DATA 280 14.3.8 Host MAC Flow Control Register (HMAC_FLOW 281 14.3.9 Host MAC VLAN1 Tag Register (HMAC_VLAN1 283 Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 8 DATASHEET Datasheet SMSC LAN9311/LAN9311i ...
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... Switch Engine ALR Read Data 0 Register (SWE_ALR_RD_DAT_0)........................................................................................................... 372 14.5.3.5 Switch Engine ALR Read Data 1 Register (SWE_ALR_RD_DAT_1)........................................................................................................... 373 14.5.3.6 Switch Engine ALR Command Status Register (SWE_ALR_CMD_STS) .................................................................................................... 375 14.5.3.7 Switch Engine ALR Configuration Register (SWE_ALR_CFG) .................................................................................................................... 376 SMSC LAN9311/LAN9311i 9 DATASHEET Revision 1.7 (06-29-10) ...
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... Power-On Configuration Strap Valid Timing 446 15.5.4 PIO Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 15.5.5 PIO Burst Read Cycle Timing 448 15.5.6 RX Data FIFO Direct PIO Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449 Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 10 DATASHEET Datasheet SMSC LAN9311/LAN9311i ...
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... TX Data FIFO Direct PIO Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452 15.5.10 Microwire Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 15.6 Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 Chapter 16 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 16.1 128-VTQFP Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 16.2 128-XVTQFP Package Outline 457 Chapter 17 Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 SMSC LAN9311/LAN9311i 11 DATASHEET Revision 1.7 (06-29-10) ...
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... List of Figures Figure 2.1 Internal LAN9311/LAN9311i Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 2.2 System Block Diagram Figure 3.1 LAN9311 128-VTQFP Pin Assignments (TOP VIEW Figure 3.2 LAN9311/LAN9311i 128-XVTQFP Pin Assignments (TOP VIEW Figure 4.1 PME and PME_INT Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 5.1 Functional Interrupt Register Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 6 ...
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... Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Figure 14.1 LAN9311/LAN9311i Base Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Figure 15.1 Output Equivalent Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 Figure 15.2 nRST Reset Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 Figure 15.3 Power-On Configuration Strap Latching Timing 446 Figure 15 ...
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... Table 3.8 PLL Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 3.9 Core and I/O Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 3.10 No-Connect Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 4.1 Reset Sources and Affected LAN9311/LAN9311i Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 4.2 Soft-Strap Configuration Strap Definitions Table 4.3 Hard-Strap Configuration Strap Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 6.1 Switch Fabric Flow Control Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 6 ...
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... Table 15.13TX Data FIFO Direct PIO Write Cycle Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452 Table 15.14Microwire Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 Table 15.15LAN9311/LAN9311iCrystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 Table 16.1 LAN9311 128-VTQFP Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 Table 16.2 LAN9311/LAN9311i 128-XVTQFP Dimensions 458 Table 17.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 SMSC LAN9311/LAN9311i 15 DATASHEET ...
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... Ethernet frame, used for error detection and correction. First In First Out buffer Finite State Machine General Purpose I/O Host Bus Interface. The physical bus connecting the LAN9311/LAN9311i to the host. Also referred to as the Host Bus. Host Bus Interface Controller. The hardware module that interfaces theLAN9311/LAN9311i to the HBI. ...
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... Not Applicable No Connect Organizationally Unique Identifier Refers to data output from the LAN9311/LAN9311i to the host Program I/O cycle. An SRAM-like read or write cycle on the HBI. Parallel In Serial Out Phase Locked Loop Precision Time Protocol Refers to a reserved bit field or address ...
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... Unless otherwise noted in the pin description, internal pull-downs are always enabled. Note: Internal pull-down resistors prevent unconnected inputs from floating. Do not rely on internal resistors to drive signals external to the LAN9311/LAN9311i. When connected to a load that must be pulled low, an external resistor must be added. AI Analog input ...
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... Many of these register bit notations can be combined. Some examples of this are shown below: R/W: Can be written. Will return current setting on a read. R/WAC: Will return current setting on a read. Writing anything clears the bit. SMSC LAN9311/LAN9311i Table 1.2 Register Bit Types REGISTER BIT DESCRIPTION ...
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... MACs and PHYs support full/half duplex 10BASE-T and 100BASE-TX operation. The LAN9311/LAN9311i provides 2 on-chip PHYs, 1 Virtual PHY and 3 MACs. The Virtual PHY and the Host MAC are used to connect the LAN9311/LAN9311i switch fabric to the host bus interface. All ports support automatic or manual full duplex flow control or half duplex backpressure (forced collision) flow control ...
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... System Clocks/ Time Stamp Interrupt Reset/PME Clock/Events Controller Free-Run Controller Clk IRQ External 25MHz Crystal Figure 2.1 Internal LAN9311/LAN9311i Block Diagram Virtual PHY MII Registers Host MAC MDIO TX/RX FIFOs Host Bus Interface Register To 16-bit Access Host Bus MUX EEPROM Loader ...
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... Pin Reset A multi-module reset is initiated by assertion of the following: Digital Reset - DIGITAL_RST (bit 0) in the - Resets all LAN9311/LAN9311i sub-modules except the Ethernet PHYs (Port 1 PHY, Port 2 PHY, and Virtual PHY) Soft Reset - SRST (bit 0) in the - Resets the HBI, Host MAC, and System CSRs below address 100h ...
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... Ethernet PHYs The LAN9311/LAN9311i contains three PHYs: Port 1 PHY, Port 2 PHY and a Virtual PHY. The Port 1 & 2 PHYs are identical in functionality and each connect their corresponding Ethernet signal pins to the switch fabric MAC of their respective port. These PHYs interface with their respective MAC via an internal MII interface ...
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... Time stamping is supported on all ports, with an individual IEEE 1588 Time Stamp module connected to each port via the MII bus. Any port may function as a master or a slave clock per the IEEE 1588 specification, and the LAN9311/LAN9311i as a whole may function as a boundary clock. ...
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... LAN9311/LAN9311i system configuration and status registers. The LAN9311/LAN9311i utilizes the internal Host MAC to provide a network path for the host CPU. The LAN9311/LAN9311i may share the host bus with additional system memory and/or peripherals. For more information on the HBI, refer to Chapter 8, " ...
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... RXN2 124 VDD33A2 125 TXP2 126 TXN2 127 VSS 128 Figure 3.1 LAN9311 128-VTQFP Pin Assignments (TOP VIEW) Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface SMSC LAN9311 128-VTQFP TOP VIEW 26 DATASHEET Datasheet VDD33IO ...
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... RXP2 123 RXN2 124 VDD33A2 125 TXP2 126 TXN2 127 VSS 128 Figure 3.2 LAN9311/LAN9311i 128-XVTQFP Pin Assignments (TOP VIEW) SMSC LAN9311/LAN9311i SMSC LAN9311/LAN9311i 128-XVTQFP TOP VIEW VSS NOTE: EXPOSED PAD ON BOTTOM OF PACKAGE MUST BE CONNECTED TO GROUND 27 DATASHEET VDD33IO 64 63 IRQ ...
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... Pin Descriptions This section contains the descriptions of the LAN9311/LAN9311i pins. The pin descriptions have been broken into functional groups as follows: LAN Port 1 Pins LAN Port 2 Pins LAN Port 1 & 2 Power and Common Pins Host Bus Interface Pins EEPROM Pins Dedicated Configuration Strap Pins ...
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... EXRES AI Bias Reference: Used for internal bias circuits. Connect to an external 12.4K ohm, 1% resistor to ground. VDD33A1 P +3.3V Port 1 Analog Power Supply Refer to the LAN9311/LAN9311i application note for additional connection information. 29 DATASHEET DESCRIPTION (LED_CFG), LED Configuration Register General Purpose I/O Configuration and General Purpose I/O (GPIO_DATA_DIR) ...
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... Refer to the LAN9311/LAN9311i application note for additional connection information. P +1.8V Port 1 Transmitter Power Supply: This pin must be connected directly to the VDD18TX2 pin for proper operation. Refer to the LAN9311/LAN9311i application note for additional connection information. Table 3.4 Host Bus Interface Pins BUFFER SYMBOL TYPE ...
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... SYMBOL TYPE IS Data FIFO Direct Access Select: When driven high, all accesses to the LAN9311/LAN9311i are directed to the RX and TX Data FIFO’s. All reads are from the RX Data FIFO, and all writes are to the TX Data FIFO. In this mode, the address input is ignored. Refer to Access Mode," ...
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... EEPROM and is recommended if no EEPROM is attached. Section 2 138. This bit is not used for I C Note 3. mode (EEPROM_TYPE=1), this pin is not used and is driven low. Section 138. See Note 3.4. Section 15.5.2, "Reset and Section 15.5.2, "Reset and 2 C mode. SMSC LAN9311/LAN9311i Section ...
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... Note 3.6 Configuration strap values are latched on power-on reset or nRST de-assertion. Configuration strap pins are identified by an underlined symbol name. Some configuration straps can be overridden by values from the EEPROM Loader. Refer to "Configuration Straps," on page 40 SMSC LAN9311/LAN9311i BUFFER SYMBOL TYPE LED_EN ...
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... Register Chapter 5, "System Interrupts," on page nRST IS System Reset Input: This active low signal allows external hardware to reset the LAN9311/LAN9311i. (PU) The LAN9311/LAN9311i also contains an internal power-on reset circuit. Thus, this signal may be left unconnected if an external hardware reset is not needed. When used, this signal must adhere to the reset timing requirements as detailed in 15.5.2, " ...
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... P Digital Core +1.8V Power Supply Output: +1.8V power from the internal core voltage regulator. All VDD18CORE pins must be tied together for proper operation. Refer to the LAN9311/LAN9311i application note for additional connection information. VSS P Common Ground Table 3.10 No-Connect Pins ...
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... Resets The LAN9311/LAN9311i provides multiple hardware and software reset sources, which allow varying levels of the LAN9311/LAN9311i to be reset. All resets can be categorized into three reset types as described in the following sections: Chip-Level Resets —Power-On Reset (POR) —nRST Pin Reset Multi-Module Resets — ...
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... READY bit is cleared. Writes to any address are invalid until the READY bit is set. Note: The LAN9311/LAN9311i must be read at least once after any chip-level reset to ensure that write operations function properly. SMSC LAN9311/LAN9311i ...
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... Power-On Reset (POR) A power-on reset occurs whenever power is initially applied to the LAN9311/LAN9311i the power is removed and reapplied to the LAN9311/LAN9311i. This event resets all circuitry within the device. Configuration straps are latched, and the EEPROM Loader is run as a result of this reset. ...
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... Reset bit in the Upon completion of the Port 2 PHY reset, the PHY2_RST and Reset bits are automatically cleared. No other modules of the LAN9311/LAN9311i are affected by this reset. In addition to the methods above, the Port 2 PHY is automatically reset after returning from a PHY power-down mode. This reset differs in that the PHY power-down mode reset does not reload or reset any of the PHY registers ...
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... Configuration Straps Configuration straps allow various features of the LAN9311/LAN9311i to be automatically configured to user defined values. Configuration straps can be organized into two main categories: hard-straps and soft-straps. Both hard-straps and soft-straps are latched upon Power-On Reset (POR) or pin reset (nRST). The primary difference between these strap types is that soft-strap default values can be overridden by the EEPROM Loader, while hard-straps cannot ...
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... Advertisement Register (PHY_AN_ADV_x) MODE[2:0] bits of the (PHY_SPECIAL_MODES_x) Refer to the respective register definition sections for additional information. SMSC LAN9311/LAN9311i LED Configuration Register One pin configures the default for all 8 LED/GPIOs, but 8 separate bits are loaded by the EEPROM Loader, allowing individual control over each LED/GPIO ...
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... Section Port x PHY Basic Control Port x PHY Auto- Port x PHY Special Modes Register Port 1 Backpressure Enable bit of the Port 1 Manual Flow Control Register Port 1 Full-Duplex and (MANUAL_FC_1), 42 DATASHEET Datasheet PIN / DEFAULT VALUE 1b bit in 14.4.2.1). 1b 14.4.2.1 Port 1 Full- bits in the SMSC LAN9311/LAN9311i ...
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... Full Duplex (bit 6) and 10BASE-T Half Duplex (bit 5) bits of the Advertisement Register (PHY_AN_ADV_x) MODE[2:0] bits of the (PHY_SPECIAL_MODES_x) Refer to the respective register definition sections for additional information. SMSC LAN9311/LAN9311i Port 1 Full-Duplex Manual Flow Control bit in the Port 1 Manual Flow (MANUAL_FC_1). When configured low, is set). and ...
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... Section Port x PHY Basic Control Port x PHY Auto- Port x PHY Special Modes Register Port 2 Backpressure Enable bit of the Port 2 Manual Flow Control Register Port 2 Full-Duplex and (MANUAL_FC_2), 44 DATASHEET Datasheet PIN / DEFAULT VALUE 1b bit in 14.4.2.1). 1b 14.4.2.1 Port 2 Full- bits in the SMSC LAN9311/LAN9311i ...
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... These straps, along with their pin assignments are also fully defined in Chapter 3, "Pin Description and Configuration," on page SMSC LAN9311/LAN9311i Port 2 Full-Duplex Manual Flow Control bit in the Port 2 Manual Flow (MANUAL_FC_2) ...
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... Power Management The LAN9311/LAN9311i Port 1 and Port 2 PHYs and the Host MAC support several power management and wakeup features. The LAN9311/LAN9311i can be programmed to issue an external wake signal (PME) via several methods, including wake on LAN, wake on link status change (energy detect), and magic packet wakeup ...
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... IRQ interrupt output pin, as described in on page 52. Refer to Section 7.2.9.2, "PHY Energy Detect Power-Down," on page 95 operation and configuration of the PHY energy-detect power-down mode. SMSC LAN9311/LAN9311i WOL_EN (bit 9) of PMT_CTRL register WOL_STS (bit 5) of PMT_CTRL register ED_EN1 (bit 14) of ...
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... Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface (PMT_CTRL). Power Management Control Register (PMT_CTRL) (PMT_CTRL). 53. for additional details on these features. 48 DATASHEET Datasheet Power Host (via the WUEN bit for wake-up frames, will be set. These Power Section and Section 9.5.1, "Magic Packet SMSC LAN9311/LAN9311i ...
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... LAN9311/LAN9311i provides a multi-tier programmable interrupt structure which is controlled by the System Interrupt Controller. The programmable system interrupts are generated internally by the various LAN9311/LAN9311i sub-modules and can be configured to generate a single external host interrupt via the IRQ interrupt output pin. The programmable nature of the host interrupt provides the user with the ability to optimize performance dependent upon the application requirements ...
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... SWE_IMR of SW_IPR register SWE_IPR Port [2,1,0] MAC Interrupt Registers Bits [2,1,0] (MAC_[2,1,MII]) MAC_IMR_[2,1,MII] of SW_IPR register MAC_IPR_[2,1,MII] Port 2 PHY Interrupt Registers PHY_INTERRUPT_SOURCE_2 PHY_INTERRUPT_MASK_2 Port 1 PHY Interrupt Registers PHY_INTERRUPT_SOURCE_1 PHY_INTERRUPT_MASK_1 Power Management Control Register PMT_CTRL GPIO Interrupt Register GPIO_INT_STS_EN 50 DATASHEET Datasheet SMSC LAN9311/LAN9311i ...
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... The following sections detail each category of interrupts and their related registers. Refer to Chapter 14, "Register Descriptions," on page 167 5.2.1 1588 Time Stamp Interrupts Multiple 1588 Time Stamp interrupt sources are provided by the LAN9311/LAN9311i. The top-level 1588_EVNT (bit 29) of the event occurred in the The 1588 Interrupt Status and Enable Register (1588_INT_STS_EN) status of all 1588 interrupt conditions ...
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... For additional details on the Ethernet PHY interrupts, refer to page 94. 5.2.4 GPIO Interrupts Each GPIO[11:0] of the LAN9311/LAN9311i is provided with its own interrupt. The top-level GPIO (bit 12) of the Interrupt Status Register (INT_STS) in the General Purpose I/O Interrupt Status and Enable Register Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN) and status of each GPIO[11:0] interrupt ...
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... Interrupt Status Register (INT_STS) on page 175 for additional information on bit definitions and Host MAC operation. 5.2.6 Power Management Interrupts Multiple Power Management Event interrupt sources are provided by the LAN9311/LAN9311i. The top- level PME_INT (bit 17) of the Management interrupt event occurred in the The Power Management Control Register (PMT_CTRL) Power Management conditions ...
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... A device ready interrupt is provided in the top-level Enable Register (INT_EN). The READY interrupt (bit 30) of the indicates that the LAN9311/LAN9311i is ready to be accessed after a power-up or reset condition. Writing this bit in the In order for a device ready interrupt event to trigger the external IRQ interrupt pin, bit 30 of the ...
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... Functional Overview At the core of the LAN9311/LAN9311i is the high performance, high efficiency 3 port Ethernet switch fabric. The switch fabric contains a 3 port VLAN layer 2 switch engine that supports untagged, VLAN tagged, and priority tagged frames. The switch fabric provides an extensive feature set which includes ...
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... Table 8.1, “Read After Write Timing Rules,” on page 103 56 DATASHEET Datasheet for writing sequential register Switch Fabric address range automatically set Switch Fabric address range, a sub-set of the Table 14.3, “Switch Fabric CSR to 241. are required where SMSC LAN9311/LAN9311i ...
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... The user should clear the AUTO_INC and AUTO_DEC bits before reading the last data to avoid an unintended read cycle. Figure 6.2 illustrates the process required to perform a switch fabric CSR read. The minimum wait periods as specified in noted. SMSC LAN9311/LAN9311i CSR Write Auto Increment / Decrement Idle Write ...
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... CSR_BUSY = 0 CSR_BUSY = 0 last data? Register Yes Write Command Register Read Data Register (MANUAL_FC_MII)). Table 6.1 58 DATASHEET Datasheet min wait period CSR_BUSY = 1 Read Data No Register (Port 1 Manual Flow Control Register (MANUAL_FC_2), or Port 0(Host MAC) details the switch fabric flow control SMSC LAN9311/LAN9311i ...
Page 59
... Advertisement Register (VPHY_AN_ADV) Base Page Ability Register "Virtual PHY Auto-Negotiation," on page 96 SMSC LAN9311/LAN9311i Port x PHY Auto-Negotiation Advertisement Register an d Virtual PHY egotia tio n Advertisement Register are not affected by the values of the manual flow control register. Refer to ...
Page 60
... Flow Control packet will be loaded into the pause counter. The pause function is enabled by either Auto-negotiation, or manually as discussed in Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 60 DATASHEET Datasheet Section 6.2.3, SMSC LAN9311/LAN9311i ...
Page 61
... Total alignment errors Total bytes received from all packets Total bytes received from good packets Total packets with a symbol error Total MAC control packets SMSC LAN9311/LAN9311i 58. Pause frames are consumed by the MAC and not sent to (MAC_RX_CFG_x). (Section 14.5.2.3, on page 326) (Section 14.5.2.4, on page (Section 14 ...
Page 62
... DATASHEET Datasheet Port x MAC Table 14.12, “Indirectly and Section 14.5.2.25 through 351) 352) 353) 354) 355) 356) 358) SMSC LAN9311/LAN9311i ...
Page 63
... Bit Age / Valid Static Filter Override SMSC LAN9311/LAN9311i (Section 14.5.2.37, on page 360) (Section 14.5.2.38, on page (Section 14.5.2.39, on page (Section 14.5.2.40, on page (Section 14.5.2.41, on page (Section 14.5.2.42, on page 365) Switch Engine ALR Write Data 0 Register and Switch Engine ALR Write Data 1 Register (SWE_ALR_WR_DAT_1) ...
Page 64
... Register (SWE_ALR_WR_DAT_1). Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface (SWE_PORT_INGRSS_CFG). for additional details Switch Engine ALR Command Register (SWE_ALR_WR_DAT_0), and 64 DATASHEET Datasheet Switch Engine Port (SWE_ALR_CMD_STS), Switch Switch Engine ALR Write Data 1 SMSC LAN9311/LAN9311i ...
Page 65
... Switch Engine ALR Command Register (SWE_ALR_CMD) Next Entry bit step 3. Note: Refer to Section 14.5.3.1, on page 368 definitions of these registers. SMSC LAN9311/LAN9311i with the desired MAC address and control Switch Engine ALR Command Status Register until it is cleared. Switch Engine ALR Command Register (SWE_ALR_RD_DAT_0), and Switch Engine ALR Read Data 1 Register until either are set ...
Page 66
... Enable Membership Checking is set. A NULL membership will also result in the packet being filtered if the destination address is not found in the ALR table (since the packet would have no destinations). Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface is in effect effect). 66 DATASHEET Datasheet Spanning Tree Spanning Tree SMSC LAN9311/LAN9311i ...
Page 67
... Source Port port default table programmable Priority 3b VLAN Priority Regeneration table per port 2b ALR Priority Figure 6.4 Switch Engine Transmit Queue Selection SMSC LAN9311/LAN9311i ALR Static Bit 3b DA Highest Priority programmable priority Traffic Class 3b calculation table 3b 67 DATASHEET Figure 6.4, the priority may ...
Page 68
... Resolved Priority = Resolved Priority = Default Priority[Source DIFFSERV[TOS] DIFFSERV[TC] Traffic Class[Resolved Priority] Get Queue Done 68 DATASHEET Datasheet Get Queue Highest N Priority Y ALR Static Bit N VL Higher Priority Y Y Packet is Tagged N & Use Packet is Tagged N Resolved Priority = Priority Regen[VLAN Port] Priority] Queue = SMSC LAN9311/LAN9311i ...
Page 69
... VLAN Priority Regeneration Table Register 2 Ingress VLAN Priority Regeneration Table Register Section 14.5.3.33, on page 403 these registers. SMSC LAN9311/LAN9311i 6.5, the default priority is based on the ingress ports priority bits in its port VID Switch Engine VLAN Write Data Register (SWE_VLAN_RD_DATA), and Section 14.5.3.8, on page 377 for detailed VLAN register descriptions ...
Page 70
... The host CPU should discard received packets from this port when in the Disabled state. Note: There is no hardware distinction between the Blocking and Disabled states. 70 DATASHEET Datasheet ... 11 0 VID for detailed VLAN (Section (Section 6.4.10, on page 75). is used to place a port into one of the Software Action SMSC LAN9311/LAN9311i ...
Page 71
... Ingress Flow Metering and Coloring The LAN9311/LAN9311i supports hardware ingress rate limiting by metering packet streams and marking packets as either Green, Yellow, or Red according to three traffic parameters: Committed Information Rate (CIR), Committed Burst Size (CBS), and Excess Burst Size (EBS). A packet is marked Green if it does not exceed the CBS, Yellow if it exceeds to CBS but not the EBS, or Red otherwise ...
Page 72
... Section 14.5.3.29, on page 399 Figure 6.7, the priority can be based on: 72 DATASHEET Datasheet Bandwidth 100 Mbps 80 Mbps 67 Mbps 57 Mbps 50 Mbps 40 Mbps 31 Mbps 20 Mbps 10 Mbps 5 Mbps 2.5 Mbps 1 Mbps 500 Kbps 250 Kbps 100 Kbps 50 Kbps for detailed register SMSC LAN9311/LAN9311i ...
Page 73
... The ingress flow calculation is based on the packet type and the device configuration as shown in Figure 6.8. Y Use Precedence Flow Priority = IP Precedence Figure 6.8 Switch Engine Ingress Flow Priority Calculation SMSC LAN9311/LAN9311i Packet is IPv 4 Packet is IP Use Precedence Use IP VLAN Enable Programmable 3b DIFFSERV Table ...
Page 74
... Broadcast Storm Control In addition to ingress rate limiting, the LAN9311/LAN9311i supports hardware broadcast storm control on a per port basis. This feature is enabled via the (SWE_BCST_THROT). The allowed rate per port is specified as the number of bytes multiplied by 64 allowed to be received every 1.72 mS interval. Packets that exceed this limit are dropped. Typical ...
Page 75
... VLAN. 6.4.9 Port Mirroring The LAN9311/LAN9311i supports port mirroring where packets received or transmitted on a port or ports can also be copied onto another “sniffer” port. Port mirroring is configured using the Multiple mirrored ports can be defined, but only one sniffer port can be defined. ...
Page 76
... Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface of Port 0 should be set. in the Host MAC should be set to 8100h and the should be set to a value other than 8100h. This configuration 76 DATASHEET Datasheet Port x MAC Receive configures the switch to Host MAC VLAN2 Tag Host MAC VLAN1 SMSC LAN9311/LAN9311i ...
Page 77
... When a packet is read from the memory and sent out to the corresponding port, the used buffers are released. SMSC LAN9311/LAN9311i Buffer Manager Drop Level Register Buffer Manager Broadcast Buffer Level Register Section 6.4.6, " ...
Page 78
... Mbps 80 Mbps 65 Mbps 67 Mbps 56 Mbps 57 Mbps 49 Mbps 50 Mbps 39 Mbps 40 Mbps 30 Mbps 31 Mbps 20 Mbps 20 Mbps 10 Mbps 10 Mbps 5 Mbps 5 Mbps 2.5 Mbps 2.5 Mbps 990 Kbps 1 Mbps 490 Kbps 500 Kbps 250 Kbps 250 Kbps 98 Kbps 100 Kbps 49 Kbps 50 Kbps SMSC LAN9311/LAN9311i ...
Page 79
... Priority field of the new VLAN is changed to the egress ports default priority. When a packet is received special-tagged from a CPU port, the special tag is removed. SMSC LAN9311/LAN9311i Section 6.4.10, "Host CPU Port Special Tagging," on page Buffer Manager Egress Port Type Register must be set ...
Page 80
... VID = Default VID VID = Default VID [ingress_port] [ingress_port] Priority = Default Priority Priority = Unchanged [ingress_port Change Priority Y N [egress_port] Modify Tag VID = Unchanged Priority = Default Priority Send Packet Untouched [egress_port] 80 DATASHEET Datasheet Special Tagged Strip Tag Strip Tag Strip Tag SMSC LAN9311/LAN9311i ...
Page 81
... Buffer Manager Port 2 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_2) 6.6 Switch Fabric Interrupts The switch fabric is capable of generating multiple maskable interrupts from the buffer manager, switch engine, and MACs. These interrupts are detailed in page 51. SMSC LAN9311/LAN9311i Section 5.2.2, "Switch Fabric Interrupts," DATASHEET Revision 1.7 (06-29-10) ...
Page 82
... Functional Overview The LAN9311/LAN9311i contains three PHYs: Port 1 PHY, Port 2 PHY and a Virtual PHY. The Port 1 & 2 PHYs are identical in functionality and each connect their corresponding Ethernet signal pins to the switch fabric MAC of their respective port. These PHYs interface with their respective MAC via an internal MII interface ...
Page 83
... MII MII To Port x MAC Switch Fabric MAC Interface PHY Management MDIO Control To Host MAC Registers Interrupts To System Interrupt Controller SMSC LAN9311/LAN9311i and 100BASE-TX Receive and 10BASE-T Receive 10/100 Transmitter HP Auto-MDIX 10/100 Reciever LEDs To GPIO/LED Controller Figure 7.1 Port x PHY Block Diagram ...
Page 84
... Shaded blocks are those which are 100M PLL MII MAC 4B/5B 25MHz Interface by 4 bits Encoder 125 Mbps Serial 100M MLT-3 MLT-3 TX Driver MLT-3 CAT-5 Section 7.2.7, "MII MAC 84 DATASHEET Datasheet Scrambler 25MHz by 5 bits and PISO Magnetics Interface". Table 7.2. Each 4-bit data-nibble SMSC LAN9311/LAN9311i ...
Page 85
... MII Receive Data Valid (RXDV) 00000 /V/ INVALID, MII Receive Error (RXER) if during MII Receive Data Valid (RXDV) 00001 /V/ INVALID, MII Receive Error (RXER) if during MII Receive Data Valid (RXDV) SMSC LAN9311/LAN9311i Table 7.2 4B/5B Code Table RECEIVER INTERPRETATION 0000 DATA 0001 0010 0011 ...
Page 86
... MHz logic and the 100BASE-TX Transmitter. Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Table 7.2 4B/5B Code Table (continued) RECEIVER INTERPRETATION 86 DATASHEET Datasheet TRANSMITTER INTERPRETATION INVALID INVALID INVALID INVALID INVALID INVALID Section 7.1.1, "PHY SMSC LAN9311/LAN9311i ...
Page 87
... The 100M PLL generates multiple phases of the 125MHz clock. A multiplexer, controlled by the timing unit of the DSP, selects the optimum phase for sampling the data. This is used as the received recovered clock. This clock is used to extract the serial data from the received signal. SMSC LAN9311/LAN9311i Figure 7.3. Shaded blocks are those which are internal ...
Page 88
... Note: The PHY is connected to the switch fabric MAC via standard MII signals. Refer to the IEEE 802.3 specification for additional details. Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 88 DATASHEET Datasheet Section 7.2.7, "MII MAC SMSC LAN9311/LAN9311i ...
Page 89
... The polarity of the signal is also checked. If the polarity is reversed (local RXP is connected to RXN of the remote partner and vice versa), then this is identified and corrected. The reversed condition is indicated by the flag “XPOL“, bit 4 in SMSC LAN9311/LAN9311i Section 7.2.7, "MII MAC Port x PHY Special Control/Status Indication Register ...
Page 90
... Besides the connection speed, the PHY can advertise remote fault indication and symmetric or asymmetric pause flow control as defined in the IEEE 802.3 specification. The LAN9311/LAN9311i does not support “Next Page” capability. Many of the default advertised capabilities of the PHY are determined via configuration straps as shown in PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x)," ...
Page 91
... Advertisement Register (PHY_AN_ADV_x) x PHY Basic Control Register will be advertised. Auto-negotiation can also be disabled via software by clearing bit 12 of the PHY Basic Control Register SMSC LAN9311/LAN9311i Reset Control Register (RESET_CTL), or bit 15 of the (Section 7.2.9, "PHY Power-Down Modes," on page Port x PHY Basic Status Register (PHY_BASIC_STATUS_x) ...
Page 92
... Parallel Detection If the LAN9311/LAN9311i is connected to a device lacking the ability to auto-negotiate (i.e. no FLPs are detected able to determine the speed of the link based on either 100M MLT-3 symbols or 10M Normal Link Pulses. In this case the link is presumed to be half-duplex per the IEEE 802.3 standard. This ability is known as “ ...
Page 93
... The MII MAC Interface is responsible for the transmission and reception of the Ethernet data to and from the switch fabric MAC. The PHY is connected internally to the switch fabric MAC via standard MII signals per IEEE 802.3. SMSC LAN9311/LAN9311i Figure 7.4 (PHY_SPECIAL_CONTROL_STAT_IND_x). When AMDIXCTRL is Section 3.2, " ...
Page 94
... PHY Power-Down Modes There are two power-down modes for the PHY: PHY General Power-Down PHY Energy Detect Power-Down Note: For more information on the various power management features of the LAN9311/LAN9311i, refer to Section 4.3, "Power Management," on page Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Section 14.4.2, " ...
Page 95
... The energy detect power down feature is part of the broader power management features of the LAN9311/LAN9311i and can be used to trigger the power management event output pin (PME). This is accomplished by enabling the energy detect power-down feature of the PHY as described above, and setting the corresponding energy detect enable (bit 14 for Port 1 PHY, bit 15 for Port 2 PHY) of ...
Page 96
... Host MAC was attached to a single port PHY. This functionality is designed to allow easy and quick integration of the LAN9311/LAN9311i into designs with minimal driver modifications. The Virtual PHY provides a full bank of registers which comply with the IEEE 802.3 specification. This enables the Virtual PHY to provide various status and control bits similar to those provided by a real PHY ...
Page 97
... Disabling Auto-Negotiation Auto-negotiation can be disabled in the Virtual PHY by clearing bit 12 (VPHY_AN) of the Basic Control Register to reflect the speed (bit 13) and duplex (bit 8) of the SMSC LAN9311/LAN9311i Virtual PHY Auto-Negotiation Expansion Register Parallel Detection is used. are set to indicate the emulated link partners abilities. ...
Page 98
... Virtual PHY Resets In addition to the chip-level hardware reset (nRST) and Power-On Reset (POR), the Virtual PHY supports three block specific resets. These are is discussed in the following sections. For detailed information on all LAN9311/LAN9311i resets, refer to 7.3.2.1 Virtual PHY Software Reset via RESET_CTL The Virtual PHY can be reset via the (VPHY_RST) ...
Page 99
... System Control and Status Registers (CSRs). These registers are accessible to the host via the Host Bus Interface and allow direct (and indirect) access to all the LAN9311/LAN9311i functions. For a full list of all System CSR’s and their descriptions, refer to Control and Status Registers" ...
Page 100
... If a read to the same word is performed, the data read is invalid and should be re-read. However, this is not a fatal error. The LAN9311/LAN9311i will reset its read counters and restart a new cycle on the next read. Note: Some registers are readable as 16-bit registers. In this case, if desired, only one 16-bit read may be performed without the need to read the other word ...
Page 101
... Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet . SMSC LAN9311/LAN9311i 16-BIT LITTLE ENDIAN (END_SEL = 0) INTERNAL ORDER MSB A[ A[ HOST DATA BUS Figure 8.1 Little Endian Byte Ordering 16-BIT BIG ENDIAN (END_SEL = 1) INTERNAL ORDER MSB A[ A[ HOST DATA BUS Figure 8 ...
Page 102
... Some registers are readable during reset. The reset condition may terminate between halves of a 16- bit read pair. In this case, the LAN9311/LAN9311i does not require 16-bit read to complete the DWORD cycle. Reads to other registers during reset are not supported, and may lead to unintended behavior. ...
Page 103
... FIFO_INT RX_CFG TX_CFG HW_CFG RX_DP_CTRL RX_FIFO_INF TX_FIFO_INF PMT_CTRL GPT_CFG GPT_CNT FREE_RUN RX_DROP MAC_CSR_CMD MAC_CSR_DATA AFC_CFG 1588_CLOCK_HI_RX_CAPTURE_1 1588_CLOCK_LO_RX_CAPTURE_1 1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_1 1588_SRC_UUID_LO_RX_CAPTURE_1 1588_CLOCK_HI_TX_CAPTURE_1 1588_CLOCK_LO_TX_CAPTURE_1 SMSC LAN9311/LAN9311i Table 8.1 Read After Write Timing Rules MINIMUM WAIT TIME FOR READ FOLLOWING ANY WRITE CYCLE (IN NS 135 ...
Page 104
... Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface MINIMUM WAIT TIME FOR READ FOLLOWING ANY WRITE CYCLE (IN NS) (ASSUMING 104 DATASHEET Datasheet NUMBER OF BYTE_TEST READS OF 45NS) CYC SMSC LAN9311/LAN9311i ...
Page 105
... Table 8.1 Read After Write Timing Rules (continued) REGISTER NAME 1588_CONFIG 1588_INT_STS_EN MANUAL_FC_1 MANUAL_FC_2 MANUAL_FC_MII SWITCH_CSR_DATA SWITCH_CSR_CMD E2P_CMD E2P_DATA LED_CFG VPHY_BASIC_CTRL VPHY_BASIC_STATUS VPHY_ID_MSB VPHY_ID_LSB VPHY_AN_ADV VPHY_AN_LP_BASE_ABILITY VPHY_AN_EXP VPHY_SPECIAL_CONTROL_STATUS GPIO_CFG GPIO_DATA_DIR GPIO_INT_STS_EN SWITCH_MAC_ADDRH SWITCH_MAC_ADDRL RESET_CTL SWITCH_CSR_DIRECT_DATA SMSC LAN9311/LAN9311i MINIMUM WAIT TIME FOR READ FOLLOWING ANY WRITE CYCLE (IN NS) (ASSUMING ...
Page 106
... There are also restrictions on specific back-to-back host read operations. These restrictions concern reading specific registers after reading a resource that has side effects. In many cases there is a delay between reading the LAN9311/LAN9311i, and the subsequent indication of the expected change in the control and status register values. ...
Page 107
... Note: Some registers have restrictions on the timing of back-to-back write-read cycles. Please refer to Section 8.5.2 END_SEL A[x:1] nCS, nRD D[15:0] (OUTPUT) Figure 8.3 Functional Timing for PIO Read Operation SMSC LAN9311/LAN9311i Table 15.8, “PIO Read Cycle Timing Values,” on page for information on these restrictions. VALID VALID 107 DATASHEET 447. The cycle ends when Figure 8 ...
Page 108
... Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Table 15.9, “PIO Burst Read Cycle Timing Values,” on VALID VALID VALID VALID VALID VALID VALID 108 DATASHEET Datasheet for the AC timing VALID VALID VALID SMSC LAN9311/LAN9311i ...
Page 109
... RX Data FIFO Direct PIO Reads In this mode only A[2:1] are decoded, and any read of the LAN9311/LAN9311i will read the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is useful when the host processor must increment its address when accessing the LAN9311/LAN9311i ...
Page 110
... RX Data FIFO Direct PIO Burst Reads In this mode only A[2:1] are decoded, and any burst read of the LAN9311/LAN9311i will read the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is useful when the host processor must increment its address when accessing the LAN9311/LAN9311i ...
Page 111
... PIO Writes PIO writes are used for all LAN9311/LAN9311i write cycles. PIO writes can be performed using Chip Select (nCS) or Write Enable (nWR). A PIO write cycle begins when both nCS and nWR are asserted. The cycle ends when either or both nCS and nWR are de-asserted. Either or both of these control signals must de-assert between cycles for the period specified in Values,” ...
Page 112
... TX Data FIFO Direct PIO Writes In this mode only A[2:1] are decoded, and any write to the LAN9311/LAN9311i will write the TX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a write access. This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is useful when the host processor must increment its address when accessing the LAN9311/LAN9311i ...
Page 113
... Flow control during full-duplex mode Decoding of control frames (PAUSE command) and disabling the transmitter Generation of control frames Interface between the Host Bus Interface and the Ethernet PHYs/Switch Fabric. SMSC LAN9311/LAN9311i system registers. Configuration". This depth of buffer storage minimizes or Host MAC MII Access Register (HMAC_MII_ACC) (HMAC_MII_DATA) ...
Page 114
... VLAN tag identify the tag, and by convention are set to the value 0x8100. The last two bytes identify the specific VLAN associated with the packet and provide a priority field. The LAN9311/LAN9311i supports VLAN-tagged packets and provides two Host MAC registers, MAC VLAN1 Tag Register (HMAC_VLAN1) which are used to identify VLAN-tagged packets ...
Page 115
... Note: This filtering function is performed after any switch fabric filtering functions. The user must ensure the switch filtering is setup properly to allow packets to be passed to the Host MAC for further filtering. SMSC LAN9311/LAN9311i Standard Ethernet Frame (1518 Bytes) Source Addr. Type ...
Page 116
... Hash Filtering for physical and multicast addresses Inverse Filtering Promiscuous Pass all multicast frames. Frames with physical addresses are perfect-filtered Pass all multicast frames. Frames with physical addresses are hash- filtered and the Host MAC to form a Host MAC (HMAC_ADDRL). SMSC LAN9311/LAN9311i ...
Page 117
... Note: When wake-up frame detection is enabled via the WUEN bit of the and Status Register despite the state of the Disable Broadcast Frames (BCAST) bit in the Register (HMAC_CR). SMSC LAN9311/LAN9311i and the Host MAC Address Low Register Host MAC Control Register (HMAC_CR) Host MAC Wake-up Control and Status Register (HMAC_WUFF) ...
Page 118
... Filter 2 Offset Filter 1Offset Table 9.3, describes the byte mask’s bit fields. FILTER I BYTE MASK DESCRIPTION Table 9.4 FILTER i COMMANDS 118 DATASHEET Datasheet Filter 1 Reserved Filter 0 Command Command Filter 0 Offset Filter 0 CRC-16 Filter 2 CRC-16 shows the Filter i command register. SMSC LAN9311/LAN9311i ...
Page 119
... Host MAC examines received data for a Magic Packet. The LAN9311/LAN9311i can be programmed to notify the host of the “Magic Packet” detection with the assertion of the host interrupt (IRQ) or power management event signal (PME). Upon detection, the Magic Packet Received bit (MPR) in the HMAC_WUCSR register is set ...
Page 120
... Switch Fabric MAC Address Low Register and Switch Fabric MAC Address High Register Register Locations Written HMAC_ADDRL[7:0] SWITCH_MAC_ADDRL[7:0] HMAC_ADDRL[15:8] SWITCH_MAC_ADDRL[15:8] HMAC_ADDRL[23:16] SWITCH_MAC_ADDRL[23:16] HMAC_ADDRL[31:24] SWITCH_MAC_ADDRL[31:24] HMAC_ADDRH[7:0] SWITCH_MAC_ADDRH[7:0] HMAC_ADDRH[15:8] SWITCH_MAC_ADDRH[15:8] 120 DATASHEET Datasheet and (SWITCH_MAC_ADDRH). Order of Reception on Ethernet Figure 9.2. The values required to SMSC LAN9311/LAN9311i ...
Page 121
... For more information on the EEPROM and EEPROM Loader, refer to Master EEPROM Controller," on page 9.7 FIFOs The LAN9311/LAN9311i contains four host-accessible FIFOs (TX Status, RX Status, TX Data, and RX Data) and two internal inaccessible Host MAC TX/RX MIL FIFO’s (TX MIL FIFO, RX MIL FIFO). 9.7.1 TX/RX FIFOs The TX/RX Data and Status FIFOs store the incoming and outgoing address and data information, acting as a conduit between the host bus interface (HBI) and the Host MAC ...
Page 122
... The TX_FIF_SZ field selects the total allocation for the TX data Table 9.8 TX/RX FIFO Configurable Sizes SIZE RANGE 512 128-892 1536-13824 1920-13440 122 DATASHEET Datasheet Host MAC RX Dropped Frames Counter (HW_CFG). The field in the Hardware Table 9.9 DEFAULT 512 704 4608 10560 SMSC LAN9311/LAN9311i shows ...
Page 123
... If the actual packet length count does not match the Packet Length field as defined in the TX command, the Transmitter Error (TXE) flag is asserted. The LAN9311/LAN9311i can be programmed to start payload transmission of a buffer on a byte boundary by setting the “Data Start Offset” field in the TX command. The “Data Start Offset” field points to the actual start of the payload data within the first 8 DWORDs of the buffer. Data before the “ ...
Page 124
... The LAN9311/LAN9311i can be programmed to strip padding from the end of a transmit packet in the event that the end of the packet does not align with the host burst boundary. This feature is necessary when the LAN9311/LAN9311i is operating in a system that always performs multi-word bursts. In such cases the LAN9311/LAN9311i must guarantee that it can accept data in multiples of the Burst length regardless of the actual packet length ...
Page 125
... The buffer format is illustrated in Host Write Figure 9.4 shows the TX Buffer written into the LAN9311/LAN9311i. It should be noted that not all of the data shown in this diagram is actually stored in the TX Data FIFO. This must be taken into account when calculating the actual TX Data FIFO usage. Please refer to Actual TX Data FIFO Usage" ...
Page 126
... Buffer Size (bytes). This field indicates the number of bytes contained in the buffer following this command. This value, along with the Buffer End Alignment field, is read and checked by the LAN9311/LAN9311i and used to determine how many extra DWORDs were added to the end of the Buffer. A running count is also maintained in the LAN9311/LAN9311i of the cumulative buffer sizes for a given packet. This cumulative value is compared against the Packet Length field in the TX command ‘ ...
Page 127
... The final buffer of any transmit packet can be any length The MIL operates in store-and-forward mode and has specific rules with respect to fragmented packets. The total space consumed in the TX MIL FIFO must be limited to no more than 2KB - 3 SMSC LAN9311/LAN9311i Table 9.11 TX Command 'B' Format DESCRIPTION Table 9.12, " ...
Page 128
... DWORDs (2,036 bytes total). Any transmit packet that is so highly fragmented that it takes more space than this must be un-fragmented (by copying to a driver-supplied buffer) before the transmit packet can be sent to the LAN9311/LAN9311i. One approach to determine whether a packet is too fragmented is to calculate the actual amount of space that it will consume, and check it against 2,036 bytes ...
Page 129
... End Alignment” Buffer 1: 0-Byte “Data Start Offset” 15-Bytes of payload data 16-Byte “Buffer End Alignment” Buffer 2: 10-Byte “Data Start Offset” 17-Bytes of payload data 16-Byte “Buffer End Alignment” SMSC LAN9311/LAN9311i DESCRIPTION 129 DATASHEET Revision 1.7 (06-29-10) ...
Page 130
... Data Start Offset 17-Byte Payload Data 5-Byte End Padding Figure 9.5 TX Example 1 130 DATASHEET Datasheet Data Passed to the TX Data FIFO TX Command 'A' TX Command 'B' 79-Byte Payload TX Command 'A' 15-Byte Payload TX Command 'A' 17-Byte Payload NOTE: Extra bytes between buffers are not transmitted SMSC LAN9311/LAN9311i ...
Page 131
... TX Command 'A' Buffer End Alignment = 0 Data Start Offset = 6 First Segment = 1 Last Segment = 1 6-Byte Data Start Offset Buffer Size =183 TX Command 'B' Packet Length = 183 SMSC LAN9311/LAN9311i Memory Mapped 0 TX Command 'A' TX Command 'B' 183-Byte Payload Data 3B End Padding Figure 9.6 TX Example 2 131 DATASHEET ...
Page 132
... TX_ON bit. If the there are frames pending in the TX Data FIFO (i.e., TX Data FIFO was not purged), the transmission will resume with this data. Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Transmit Configuration Register Interrupt Status Register 132 DATASHEET Datasheet (INT_STS). SMSC LAN9311/LAN9311i ...
Page 133
... The host can set an offset from 0-31 bytes. The offset may be changed in between RX packets, but it must not be changed during an RX packet read. The LAN9311/LAN9311i can be programmed to add padding at the end of a receive packet in the event that the end of the packet does not align with the host burst boundary. This feature is necessary when the LAN9311/LAN9311i is operating in a system that always performs multi-DWORD bursts ...
Page 134
... Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface init Idle RX Interrupt Read RX Status DWORD Not Last Packet Read RX Packet init Read RX_FIFO_INF Valid Status DWORD Read RX Status DWORD Not Last Packet Read RX Packet 134 DATASHEET Datasheet SMSC LAN9311/LAN9311i ...
Page 135
... The RX data path implements an automatic data discard function. Using the RX Data FIFO Fast Forward bit (RX_FFWD) in the instruct the LAN9311/LAN9311i to skip the packet at the head of the RX Data FIFO. The RX Data FIFO pointers are automatically incremented to the beginning of the next RX packet. When performing a fast-forward, there must be at least 4 DWORDs of data in the RX Data FIFO for the packet being discarded ...
Page 136
... Runt frame late collision was detected or when the Watchdog Time-out occurs. 0 Reserved. These bits are reserved. Reads 0 Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface DESCRIPTION is set. 136 DATASHEET Datasheet SMSC LAN9311/LAN9311i ...
Page 137
... RX Error (RXE) will be asserted under the following conditions: A host underrun of RX Data FIFO A host underrun of the RX Status FIFO An overrun of the RX Status FIFO It is the duty of the host to identify and resolve any error conditions. SMSC LAN9311/LAN9311i Host MAC Control Register Interrupt Status Register (INT_STS) 137 DATASHEET (HMAC_CR) ...
Page 138
... Various commands are supported for each EEPROM type, allowing for the storage and retrieval of static data. The I The EEPROM Loader provides the automatic loading of configuration settings from the EEPROM into the LAN9311/LAN9311i at reset. The EEPROM Loader module interfaces to the EEPROM Controller, Ethernet PHYs, and the system CSRs ...
Page 139
... Note: The EEPROM device powers-up in the erase/write disabled state. To modify the contents of the EEPROM, the EWEN command must first be issued operation is attempted and the EEPROM device does not respond within 30mS, the LAN9311/LAN9311i will time-out, and the EPC_TIMEOUT bit of the (E2P_CMD) will be set. ...
Page 140
... E2P_CMD Register EEPROM Command Register (E2P_CMD) (E2P_CMD). Within each size range, the largest EEPROM uses all the 140 DATASHEET Datasheet EEPROM Read Idle Write E2P_CMD Register Read E2P_CMD Register EPC_BUSY = 0 Read E2P_DATA Register 2 C EEPROMs EEPROMs are supported. The SMSC LAN9311/LAN9311i is ...
Page 141
... Typically the receiver acknowledges each byte. If the master is the receiver, it does not generate an acknowledge on the last byte of a transfer. This informs the slave to not drive the next byte of data so that the master may generate a stop or repeated start condition. SMSC LAN9311/LAN9311i 2 C operation are shown in ...
Page 142
... C EEPROM addressing bit order for single and double byte addressing. Control Byte Chip / Block R/~W Select Bits Double Byte Addressing 2 Figure 10 EEPROM Addressing 142 DATASHEET Datasheet data data can stable change P Data Valid Stop Condition or Ack EEPROM Command Address High Address Low Byte Byte SMSC LAN9311/LAN9311i ...
Page 143
... Chip / Block R/~W Select Bits Control Byte Chip / Block R/~W Select Bits Figure 10.5 I SMSC LAN9311/LAN9311i EEPROM Command Register (E2P_CMD EEPROM byte read for single and double byte addressing. Control Byte Chip / Block Select Bits 2 Figure 10 EEPROM Byte Read EEPROM Command Register (E2P_CMD) ...
Page 144
... Chip / Block Select Bits Select Bits 2 Figure 10 EEPROM Byte Write 144 DATASHEET Datasheet Section 10.2.4, "EEPROM Loader" Section 10.2.1, "EEPROM Controller EEPROM 2 C master Conclude Poll Cycle Control Byte ... R/~W Chip / Block R/~W Select Bits Section 10.2.1, "EEPROM Controller SMSC LAN9311/LAN9311i for 2 C ...
Page 145
... Table 10.5 Microwire Command Set for 9 Address Bits START INST BIT OPCODE ERASE 1 11 ERAL 1 00 SMSC LAN9311/LAN9311i EEPROM Command Register (E2P_CMD). Within each size range, the EEPROM SIZE 7 128 256 x 8 and 512 1024 x 8 and 2048 x 8 RESERVED for detailed Microwire timing information. ...
Page 146
... EEPROM Command Register Figure 10.7 EEPROM ERASE Cycle 146 DATASHEET Datasheet DATA TO DATA FROM # OF EEPROM EEPROM CLOCKS - Hi Hi (RDY/~BSY (RDY/~BSY) 20 DATA TO DATA FROM # OF EEPROM EEPROM CLOCKS - (RDY/~BSY (RDY/~BSY Hi Hi (RDY/~BSY (RDY/~BSY) 22 (E2P_CMD). The EPC_TIMEOUT SMSC LAN9311/LAN9311i ...
Page 147
... EEDI 10.2.3.4 EWDS (Erase/Write Disable) After this command is issued, the EEPROM will ignore erase and write commands. To re-enable erase/write operations, the EWEN command must be issued. EECS EECLK EEDO 1 EEDI SMSC LAN9311/LAN9311i EEPROM Command Register (E2P_CMD Figure 10.8 EEPROM ERAL Cycle Figure 10.9 EEPROM EWDS Cycle ...
Page 148
... EEDI Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Figure 10.10 EEPROM EWEN Cycle (E2P_CMD). The result of the read is available in the Figure 10.11 EEPROM READ Cycle 148 DATASHEET Datasheet EEPROM Data D7 D0 SMSC LAN9311/LAN9311i ...
Page 149
... EPC_TIMEOUT bit of the respond within 30mS. EECS EECLK EEDO EEDI SMSC LAN9311/LAN9311i to be written to the EEPROM location pointed to by the EEPROM Command Register (E2P_CMD). The EPC_TIMEOUT bit of the is set if the EEPROM does not respond within 30mS Figure 10.12 EEPROM WRITE Cycle to be written to every EEPROM memory location ...
Page 150
... EPC_BUSY bit in the While the EEPROM Loader is active, the READY bit of the (HW_CFG) and Power Management Control Register (PMT_CTRL) LAN9311/LAN9311i should be attempted. The operational flow of the EEPROM Loader can be seen in Figure 10.14. Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface ...
Page 151
... Update LED_CFG, MANUAL_FC_1, MANUAL_FC_2 and MANUAL_FC_mii registers Read Byte 12 Byte 12 = A5h Perform register data load loop Figure 10.14 EEPROM Loader Flow Diagram SMSC LAN9311/LAN9311i N Load PHY registers with current straps Y Load PHY registers with N current straps Y Write Bytes 1-6 into Host ...
Page 152
... The EEPROM bytes are written into the MAC Table 10.7. Refer to (HW_CFG)), the EEPROM Loader will read byte 0. If the byte Table 10.8. If the flag byte is not A5h, these next 4 bytes are skipped Section for more information on the LAN9311/LAN9311i configuration Table 10.8 EEPROM Configuration Bits manual_ manual_mdix ...
Page 153
... Register Data Optionally following the configuration strap values, the EEPROM data may be formatted to allow access to the LAN9311/LAN9311i parallel, directly writable registers. Access to indirectly accessible registers (e.g. Switch Engine registers, etc.) is achievable with an appropriate sequence of writes (at the cost of EEPROM space). This data is first preceded with a Burst Sequence Valid Flag (EEPROM byte 12). If this byte has a value of A5h, the data that follows is recognized as a sequence of bursts ...
Page 154
... In order to allow the EEPROM Loader to change the Port 1/2 PHYs and Virtual PHY strap inputs and maintain consistency with the PHY and Virtual PHY registers, the following sequence is used: 1. After power-up or upon a hardware reset (nRST), the straps are sampled into the LAN9311/LAN9311i as specified in page 445. ...
Page 155
... Time stamping is supported on all ports, with an individual IEEE 1588 Time Stamp module connected to each port via the MII bus. Any port may function as a master or a slave clock per the IEEE 1588 specification, and the LAN9311/LAN9311i as a whole may function as a boundary clock. ...
Page 156
... Block Diagram The LAN9311/LAN9311i IEEE 1588 implementation is illustrated in following major function blocks: IEEE 1588 Time Stamp These three identical blocks provide time stamping functions on all switch fabric ports. IEEE 1588 Clock This block provides a 64-bit tunable clock that is used as the time source for all IEEE 1588 time stamp related functions ...
Page 157
... PHY. This is consistent with the point-of-view of where the partner clock resides (LAN9311/LAN9311i receives packets from the partner via the PHY, etc.). For the time stamp module connected to the Host MAC (Port 0), the definition of transmit and receive is reversed. Receive is defined as data from the switch fabric, while transmit is defined as data to the switch fabric ...
Page 158
... Section 11.6, "IEEE 1588 Interrupts," on page 161 1588 Interrupt Status and Enable Register 158 DATASHEET Datasheet for details on these modes. DELAY (+/- 10 nS 120 nS Port x 1588 Source UUID Low- and Port x 1588 Source UUID for information (1588_INT_STS_EN). 1588 Configuration Register is set. Refer to Section for additional information on SMSC LAN9311/LAN9311i ...
Page 159
... PTP Message Detection In order to provide the most flexibility, loose packet type matching is used by the LAN9311/LAN9311i. This assumes that for all packets received with a valid FCS, only the MAC destination address is required to qualify them as a PTP message. For Ethernet, four multicast addresses are specified in the PTP protocol: 224 ...
Page 160
... IEEE 1588 Clock The 64-bit IEEE 1588 clock is the time source for all IEEE 1588 related functions of the LAN9311/LAN9311i readable and writable by the host via the (1588_CLOCK_HI) and In order to accurately read this clock, a special procedure must be followed. Since two DWORD reads are required to fully read the 64-bit clock, the possibility exists that as the lower 32-bits roll over, a wrong intermediate value could be read ...
Page 161
... GPIO inputs must be active for greater than recognized as clear events. For more information on IEEE 1588 GPIO interrupts, refer to page 164. Refer to Chapter 5, "System Interrupts," on page 49 LAN9311/LAN9311i interrupts. SMSC LAN9311/LAN9311i 1588 Clock Target High-DWORD Register 1588 Interrupt Status and Enable Register 1588 Configuration Register (1588_CONFIG) (1588_CLOCK_TARGET_RELOAD_LO)) ...
Page 162
... This chapter details the LAN9311/LAN9311i General Purpose Timer (GPT) and the Free-Running Clock. 12.1 General Purpose Timer The LAN9311/LAN9311i provides a 16-bit programmable General Purpose Timer that can be used to generate periodic system interrupts. The resolution of this timer is 100uS. The GPT loads the GPT_LOAD field of the ...
Page 163
... Note: For GPIO[9:8], the pin direction is a function of both the GPDIR[9:8] bits of the Purpose I/O Data & Direction Register (GPIO_DATA_DIR) the General Purpose I/O Configuration Register SMSC LAN9311/LAN9311i 193. General Purpose I/O Data & Direction Register (GPIO_CFG)) Section 13.3, "LED Operation" ...
Page 164
... General Purpose I/O Configuration Register 13.2.2 GPIO Interrupts Each GPIO of the LAN9311/LAN9311i provides the ability to trigger a unique GPIO interrupt in the General Purpose I/O Interrupt Status and Enable Register GPIO_INT[11:0] bits of this register provides the current status of the corresponding interrupt, and each interrupt is enabled by setting the corresponding GPIO_INT_EN[11:0] bit ...
Page 165
... Port 0 nP1LED2 Link / Activity (GPIO2) Port 1 SMSC LAN9311/LAN9311i General Purpose I/O Interrupt Status and Enable 1588 Interrupt Status and Enable Register 1588 Interrupt Status and Enable Register (LED_CFG). These bits allow the configuration of each LED pin to indicate LED Configuration Register (LED_CFG) ...
Page 166
... Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface LED_CFG[9:8] (LED_FUN[1:0]) Full-duplex / Collision Full-duplex / Collision Port 1 Port 1 10Link / Activity Speed Port 1 Port 1 Table 13.1 are described below: 166 DATASHEET Datasheet TXEN Port 1 RXDV Port 1 SMSC LAN9311/LAN9311i ...
Page 167
... Note: Register bit type definitions are provided in Note: Not all LAN9311/LAN9311i registers are memory mapped or directly addressable. For details on the accessibility of the various LAN9311/LAN9311i registers, refer the register sub-sections listed above. ...
Page 168
... Direct FIFO Access Mode When the FIFO_SEL pin is driven high, the LAN9311/LAN9311i enters the direct FIFO access mode. In this mode, all host write operations are to the TX Data FIFO and all host read operations are from the RX Data FIFO. When FIFO_SEL is asserted, only the A[2:1] host address signals are decoded. ...
Page 169
... PMT_CTRL 088h RESERVED 08Ch GPT_CFG 090h GPT_CNT 094h - 098h RESERVED SMSC LAN9311/LAN9311i REGISTER NAME Chip ID and Revision Register, Interrupt Configuration Register, Interrupt Status Register, Interrupt Enable Register, Reserved for Future Use Byte Order Test Register, FIFO Level Interrupts Register, Receive Configuration Register, ...
Page 170
... Port 2 1588 Clock High-DWORD Transmit Capture Register, Section 14.2.5.5 Port 2 1588 Clock Low-DWORD Transmit Capture Register, Section 14.2.5.6 Port 2 1588 Sequence ID, Source UUID High-WORD Transmit Capture Register, 170 DATASHEET Datasheet Section 14.2.9.7 Section 14.2.2.8 Section 14.2.5.3 Section 14.2.5.7 Section 14.2.5.3 Section 14.2.5.7 SMSC LAN9311/LAN9311i ...
Page 171
... SMSC LAN9311/LAN9311i REGISTER NAME Port 2 1588 Source UUID Low-DWORD Transmit Capture Register, Section 14.2.5.8 Port 0 1588 Clock High-DWORD Receive Capture Register, Section 14.2.5.1 Port 0 1588 Clock Low-DWORD Receive Capture Register, Section 14.2.5.2 ...
Page 172
... Switch Engine CSR Interface Direct Data Register, Section 14.2.6.8 Reserved for Future Use 172 DATASHEET Datasheet Section 14.2.6.1 Section 14.2.6.2 Section 14.2.6.3 Section 14.2.4.1 Section 14.2.4.2 Section 14.2.3.4 Section 14.2.8.1 Section 14.2.8.2 Section 14.2.8.3 Section 14.2.8.4 Section 14.2.6.6 Section 14.2.6.7 SMSC LAN9311/LAN9311i ...
Page 173
... Datasheet 14.2.1 Interrupts This section details the interrupt related System CSR’s. These registers control, configure, and monitor the IRQ interrupt output pin and the various LAN9311/LAN9311i interrupt sources. For more information on the LAN9311/LAN9311i interrupts, refer to 14.2.1.1 Interrupt Configuration Register (IRQ_CFG) Offset: This read/write register configures and indicates the state of the IRQ signal ...
Page 174
... Configuration Register (HW_CFG) Register (RESET_CTL) Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface DESCRIPTION register or the DIGITAL_RST bit in the is set. 174 DATASHEET Datasheet TYPE DEFAULT R/W 0b NASR Note 14 R/W 0b NASR Note 14.1 Hardware Reset Control SMSC LAN9311/LAN9311i ...
Page 175
... Register (INT_EN) is set high. Writing a one clears this interrupt. 30 Device Ready (READY) This interrupt indicates that the LAN9311/LAN9311i is ready to be accessed after a power-up or reset condition. 29 1588 Interrupt Event (1588_EVNT) This bit indicates an interrupt event from the IEEE 1588 module. This bit ...
Page 176
... Section 9.8.7, "Transmitter Errors," on page 132 General Purpose TX Data Available Level (FIFO_INT). TX Status Level field of the FIFO Level Interrupt 176 DATASHEET Datasheet TYPE DEFAULT R/ R/WC 0b must first be R/WC 0b R/WC 0b R/ R/WC 0b R/WC 0b field of R/WC 0b R/ SMSC LAN9311/LAN9311i ...
Page 177
... This interrupt is generated when the RX Status FIFO is full Status FIFO Level Interrupt (RSFL) This interrupt is generated when the RX Status FIFO reaches the programmed level in the Register (FIFO_INT). 2:0 RESERVED SMSC LAN9311/LAN9311i DESCRIPTION RX Status Level field of the FIFO Level Interrupt 177 DATASHEET TYPE DEFAULT ...
Page 178
... DESCRIPTION 178 DATASHEET Datasheet 32 bits register TYPE DEFAULT R/W 0b R/W 0b R/W 0b R/W 0b R/W 0b R/W 0b R/W 0b R R/W 0b R R/W 0b R/W 0b R/W 0b R/W 0b R/W 0b R/W 0b R/W 0b R/W 0b R/W 0b R/W 0b R/W 0b R/W 0b SMSC LAN9311/LAN9311i ...
Page 179
... Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS 5 RESERVED - This bit must be written with 0b for proper operation Status FIFO Full Interrupt Enable (RSFF_EN Status FIFO Level Interrupt Enable (RSFL_EN) 2:0 RESERVED SMSC LAN9311/LAN9311i DESCRIPTION 179 DATASHEET TYPE DEFAULT R/W 0b R/W 0b R/W ...
Page 180
... Interrupt Status Register will be generated. When the TX TX Status FIFO Level Interrupt Status Register will be generated. When the RX RX Status FIFO Level Interrupt Status Register 180 DATASHEET Datasheet 32 bits TYPE DEFAULT R/W 48h R/W 00h R/W 00h R/W 00h SMSC LAN9311/LAN9311i ...
Page 181
... RX End Alignment (RX_EA) This field specifies the alignment that must be maintained on the last data transfer of a buffer. The LAN9311/LAN9311i will add extra DWORD’s of data up to the alignment specified in the table below. The host is responsible for removing these extra DWORD’s. This mechanism can be used to maintain cache line alignment on host processors ...
Page 182
... Modifications to the upper bits will take affect on the next DWORD read. 7:0 RESERVED Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface DESCRIPTION 182 DATASHEET Datasheet TYPE DEFAULT RO - R/W 00000b RO - SMSC LAN9311/LAN9311i ...
Page 183
... When this bit is set, the Host MAC transmitter will finish the current frame, and will then stop transmitting. When the transmitter has stopped this bit will clear. All writes to this bit are ignored while this bit is high. SMSC LAN9311/LAN9311i 070h Size: ...
Page 184
... Forward," on page 135 of RX_FFWD. 30:0 RESERVED Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 078h Size: DESCRIPTION Section 9.9.1.1, "Receive Data FIFO Fast for detailed information regarding the use 184 DATASHEET Datasheet 32 bits TYPE DEFAULT R SMSC LAN9311/LAN9311i ...
Page 185
... This field indicates the amount of space, in bytes, used in the RX Data FIFO. For each receive frame, the field is incremented by the length of the receive data. In cases where the payload does not end on a DWORD boundary, the total will be rounded up to the nearest DWORD. SMSC LAN9311/LAN9311i 07Ch Size: DESCRIPTION ...
Page 186
... This field indicates the amount of space, in bytes, available in the TX Data FIFO. The application should never write more than is available, as indicated by this value. Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 080h Size: DESCRIPTION 186 DATASHEET Datasheet 32 bits TYPE DEFAULT 1200h SMSC LAN9311/LAN9311i ...
Page 187
... This counter is incremented every time a receive frame is dropped by the Host MAC. RX_DFC is cleared on any read of this register. Note: The interrupt RXDFH_INT (bit 23 of the (INT_STS)) can be issued when this counter passes through its halfway point (7FFFFFFFh to 80000000h). SMSC LAN9311/LAN9311i 0A0h Size: DESCRIPTION Interrupt Status Register 187 ...
Page 188
... Size: Host MAC CSR Interface Data Register (MAC_CSR_DATA) Section 14.3, "Host MAC Control and Status 271. For more information on the Host MAC, refer to 113. DESCRIPTION (MAC_CSR_DATA). 188 DATASHEET Datasheet 32 bits Chapter 9, "Host TYPE DEFAULT R R R/W 00h 271. SMSC LAN9311/LAN9311i to ...
Page 189
... Note: The MAC_CSR_CMD and MAC_CSR_DATA registers must not be modified until the CSR Busy bit is cleared in the MAC_CSR_CMD register. SMSC LAN9311/LAN9311i 0A8h Size: Host MAC CSR Interface Command Register Section 14.3, "Host MAC Control and Status 271. For more information on the Host MAC, refer to 113 ...
Page 190
... DESCRIPTION Host MAC Flow Control Register Port 0(Host MAC) Manual Flow Control Port 0(Host MAC) Manual Flow Control Table 14.2, describing Backpressure Duration bit 190 DATASHEET Datasheet 32 bits in the Host MAC CSR TYPE DEFAULT RO - R/W 00h R/W 00h R/W 0h SMSC LAN9311/LAN9311i ...
Page 191
... Data FIFO level is reached. The MAC will queue the pause frame transmission for the next available window. Setting this bit overrides bits [3:1] of this register. Table 14.2 Backpressure Duration Bit Mapping [7: SMSC LAN9311/LAN9311i DESCRIPTION BACKPRESSURE DURATION 100Mbs Mode 5uS 10uS 15uS 25uS 50uS 100uS 150uS 200uS 250uS 191 ...
Page 192
... Table 14.2 Backpressure Duration Bit Mapping (continued Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface BACKPRESSURE DURATION 300uS 350uS 400uS 450uS 500uS 550uS 600uS 192 DATASHEET Datasheet 302.2uS 352.2uS 402.2uS 452.2uS 502.2uS 552.2uS 602.2uS SMSC LAN9311/LAN9311i ...
Page 193
... GPIO 8 Clock Event Polarity (GPIO_EVENT_POL_8) This bit determines if the 1588 clock event output on GPIO 8 is active high or low. 0: 1588 clock event output active low 1: 1588 clock event output active high SMSC LAN9311/LAN9311i 1E0h Size: DESCRIPTION 1588 Interrupt Status and Enable Register General (GPIO_INT_STS_EN) ...
Page 194
... GPIOx Clock Event Polarity Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface DESCRIPTION 1588 Clock Event Pin State no not driven yes driven low no driven low yes not driven 194 DATASHEET Datasheet TYPE DEFAULT R/W 0h SMSC LAN9311/LAN9311i ...
Page 195
... For GPIOs 11-10 and 7-0, the pin direction is determined by the GPDIR bits of this register. For GPIOs 9 and 8, the pin direction is determined by the GPDIR bits and the 1588_GPIO_OE bits in the Configuration Register (GPIO_CFG). SMSC LAN9311/LAN9311i 1E4h Size: DESCRIPTION General Purpose I/O 195 ...
Page 196
... Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 1E8h Size: Interrupt Status Register Interrupt Enable Register (INT_EN) Chapter 5, "System Interrupts," on page 49 DESCRIPTION in order to cause the General Purpose I/O Configuration 196 DATASHEET Datasheet 32 bits (INT_STS). Writing a 1 must also be set in order TYPE DEFAULT R/WC 0h SMSC LAN9311/LAN9311i for ...
Page 197
... Note 14.3 The default value of this field is determined by the configuration strap LED_en_strap[7:0]. Configuration strap values are latched on power-on reset or nRST de-assertion. Some configuration straps can be overridden by values from the EEPROM Loader. Refer to Section 4.2.4, "Configuration Straps," on page 40 SMSC LAN9311/LAN9311i 1BCh Size: DESCRIPTION 165 ...
Page 198
... EEPROM This section details the EEPROM related System CSR’s. These registers should only be used if an EEPROM has been connected to the LAN9311/LAN9311i. Refer to chapter "I2C/Microwire Master EEPROM Controller," on page 138 2 modes (I C and Microwire) of the EEPROM Controller (EPC). 14.2.4.1 ...
Page 199
... RELOAD operation will fail. The CFG_LOADED bit indicates a successful load. Following this command, the device will enter the not ready state. The READY bit in the Hardware Configuration Register (HW_CFG) to determine then the RELOAD is complete. 27:19 RESERVED SMSC LAN9311/LAN9311i DESCRIPTION [28] Operation 0 READ 1 ...
Page 200
... This field is used by the EEPROM Controller to address a specific memory location in the serial EEPROM. This address must be byte aligned. Revision 1.7 (06-29-10) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface DESCRIPTION 200 DATASHEET Datasheet TYPE DEFAULT RO 0b R/WC 0b R/WC 0b R/W 0000h SMSC LAN9311/LAN9311i ...